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1. 发明申请

US20110193136A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110193136A1
公开(公告)日：2011-08-11
申请号：US13024004
申请日：2011-02-09
申请人： Masashige MORITOKI , Takamasa ITOU , Takashi OGURA , Tsutomu HIMUKAI , Shigeaki SHIMIZU
发明人： Masashige MORITOKI , Takamasa ITOU , Takashi OGURA , Tsutomu HIMUKAI , Shigeaki SHIMIZU
IPC分类号： H01L23/522
CPC分类号： H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.
摘要翻译：为了提供一种在抑制逻辑电路的接触电阻的增加的同时最大限度地实现存储电路的电容器电容的增加的半导体器件的结构及其制造方法。当将具有构成逻辑电路区域的布线的局部互连层的层数指定为M并且指定具有构成存储器电路的布线的局部互连层的层数为N（M和N为自然数并且满足M> N），在由（M-N）层或（M-N + 1）层组成的互连层上提供电容元件。

2. 发明申请

US20050222882A1 Quality problem treatment supporting system 审中-公开
标题翻译：质量问题处理配套制度
公开(公告)号：US20050222882A1
公开(公告)日：2005-10-06
申请号：US11094566
申请日：2005-03-30
申请人： Mariko Aoki , Takamasa Itou , Daisuke Mamiya
发明人： Mariko Aoki , Takamasa Itou , Daisuke Mamiya
IPC分类号： G06Q30/02 , G06F7/00 , G06F17/30 , G06Q10/00 , G06Q50/00 , G06F17/60
CPC分类号： G06Q30/02 , G06Q10/06395 , G06Q10/20 , G06Q30/014
摘要： A quality problem treatment supporting system includes a storage portion and a processing portion. The processing portion includes a claim code checking program; a parts number checking program; an attached file search program; a temporal registration data determination program; a claim history data determination program; a delivery result search program; a classification data generation program; an investigation-execution-section determination section; a formal registration execution program; an investigation request message generation program; a past status determination program; a continuous failure determination program; a post-processing data generation program; a defect responsibility rate calculation program; a price data extraction program; an expense data extraction program; a remuneration calculation program; a monetary amount calculation program; and an payment amount determination program; and a monetary amount information transmission program.
摘要翻译：质量问题处理支持系统包括存储部分和处理部分。处理部分包括权利要求代码检查程序; 零件编号检查程序; 附件文件搜索程序; 时间登记数据确定程序; 索赔历史数据确定程序; 送货结果搜索程序; 分类数据生成程序; 调查执行部确定部; 正式的注册执行程序; 调查请求消息生成程序; 过去的地位确定计划; 连续故障确定程序; 后处理数据生成程序; 缺陷责任率计算程序; 价格数据提取程序; 费用数据提取程序; 薪酬计算方案; 货币计算方案; 和付款金额确定程序; 和货币信息传输程序。

3. 发明授权

US07585771B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07585771B2
公开(公告)日：2009-09-08
申请号：US11409061
申请日：2006-04-24
申请人： Tomoko Matsuda , Takamasa Itou
发明人： Tomoko Matsuda , Takamasa Itou
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.
摘要翻译：制造半导体器件的方法包括：通过利用预定的温度曲线，在溅射设备中的硅衬底的器件形成表面上形成一价二钴二钴（Co 2 Si）或钴（Co）层; 将硅衬底的温度升高到在形成Co或Co 2 Si层之后进行的等于或高于600℃的预定温度T2; 在硅衬底加热到T2之后，在等于或高于T2的温度下，在硅衬底的器件形成表面上形成一层单铁（CoSi）层，其中硅衬底升高到在形成Co或Co 2 Si层期间的硅衬底的最高可达到的温度T1和在等于或高于50℃/ sec的温度斜率下的温度T2。

4. 发明授权

US09136035B2 Flexible conductive material and transducer, flexible wiring board, and electromagnetic shield using the same 有权
标题翻译：柔性导电材料和换能器，柔性线路板和使用其的电磁屏蔽
公开(公告)号：US09136035B2
公开(公告)日：2015-09-15
申请号：US13489860
申请日：2012-06-06
申请人： Takamasa Itou , Jun Kobayashi , Hitoshi Yoshikawa
发明人： Takamasa Itou , Jun Kobayashi , Hitoshi Yoshikawa
IPC分类号： H01B1/20 , H01B1/22 , H01B1/24 , H02N11/00 , H05K1/02 , H05K9/00 , H01L41/08 , H01L41/113 , H05K1/03 , C08K3/04 , H05K1/16
CPC分类号： H01B1/22 , C08K3/04 , H01B1/24 , H01L41/0805 , H01L41/113 , H05K1/0256 , H05K1/0373 , H05K1/162 , H05K2201/0133 , H05K2201/0323 , C08L15/005
摘要： A flexible conductive material includes an elastomer, a conductive agent filled in the elastomer, and an adsorbent fixed inside the elastomer and able to adsorb ionic material. With the flexible conductive material, ionized impurities are unlikely to transfer to an adherend such as a dielectric film. Thus, leakage current during application of voltage decreases. Accordingly, by forming an electrode and a wiring with the flexible conductive material, leakage current can be reduced, and a transducer and a flexible wiring board having excellent durability can be produced. In addition, using the flexible conductive material, an electromagnetic shield can be produced having a small leakage current.
摘要翻译：柔性导电材料包括弹性体，填充在弹性体中的导电剂和固定在弹性体内部并能够吸附离子材料的吸附剂。对于柔性导电材料，电离杂质不可能转移到诸如电介质膜的被粘物上。因此，施加电压期间的漏电流降低。因此，通过用柔性导电材料形成电极和布线，可以降低泄漏电流，并且可以产生具有优异耐久性的换能器和柔性布线板。此外，使用柔性导电材料，可以制造具有小的漏电流的电磁屏蔽。

5. 发明申请

US20060240667A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060240667A1
公开(公告)日：2006-10-26
申请号：US11409061
申请日：2006-04-24
申请人： Tomoko Matsuda , Takamasa Itou
发明人： Tomoko Matsuda , Takamasa Itou
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.
摘要翻译：制造半导体器件的方法包括：通过利用溅射装置在硅衬底的器件形成表面上形成一价二钴二钴（Co 2 Si 2 Si）或钴（Co）层预定的温度曲线; 将硅衬底的温度升高到在形成Co或Co 2 Si层之后进行的等于或高于600℃的预定温度T 2; 在硅衬底加热到T 2之后，在等于或高于T 2的温度下，在硅衬底的器件形成表面上形成一层单铁（CoSi）层，其中将硅衬底升高到在形成Co或Co 2 Si层之间的硅衬底的最高可达到的温度T 1与温度升高速率等于或高于50℃的温度之间的温度。秒

6. 发明授权

US08368176B2 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US08368176B2
公开(公告)日：2013-02-05
申请号：US13157020
申请日：2011-06-09
申请人： Takayuki Iwaki , Takamasa Itou , Kana Shimizu
发明人： Takayuki Iwaki , Takamasa Itou , Kana Shimizu
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L21/02244 , H01L21/02252 , H01L21/02356 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

7. 发明申请

US20110304017A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110304017A1
公开(公告)日：2011-12-15
申请号：US13157020
申请日：2011-06-09
申请人： Takayuki IWAKI , Takamasa ITOU , Kana SHIMIZU
发明人： Takayuki IWAKI , Takamasa ITOU , Kana SHIMIZU
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L21/02244 , H01L21/02252 , H01L21/02356 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.
摘要翻译：下电极在表层具有厚度为2nm以下的含金属氧化物层。通过氧化下电极的表面形成含金属氧化物层。电介质膜包括在体状态下出现在室温的第一相和在大体积状态下出现在比第一相高的温度的第二相。第二相具有比第一相高的相对介电常数。

8. 发明授权

US07786005B2 Method for manufacturing semiconductor device to form a via hole 有权
标题翻译：制造半导体器件以形成通孔的方法
公开(公告)号：US07786005B2
公开(公告)日：2010-08-31
申请号：US11369955
申请日：2006-03-08
申请人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
发明人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
IPC分类号： H01L21/467
CPC分类号： H01L21/02063 , H01L21/76814
摘要： An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
摘要翻译：由于可以有效地防止在形成通孔之后形成和生长的改变层的存在而导致的通孔电阻的增加，从而提供了半导体器件的改进的可靠性。一种方法包括：在半导体衬底上形成TiN膜; 在TiN膜的表面上形成层间绝缘膜; 在所述层间绝缘膜的表面上形成抗蚀剂膜; 蚀刻其上形成有抗蚀剂膜的半导体衬底以形成开口，从而部分地暴露TiN膜; 等离子体处理TiN膜的暴露部分以去除在TiN膜的暴露部分中形成的改变的层; 并通过高温等离子体处理剥离抗蚀剂膜。

9. 发明授权

US07687918B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07687918B2
公开(公告)日：2010-03-30
申请号：US10740813
申请日：2003-12-22
申请人： Yorinobu Kunimune , Mieko Hasegawa , Takamasa Itou , Takeshi Takeda , Hidemitsu Aoki
发明人： Yorinobu Kunimune , Mieko Hasegawa , Takamasa Itou , Takeshi Takeda , Hidemitsu Aoki
IPC分类号： H01L23/48
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76808 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.
摘要翻译：本发明提供一种半导体器件，其包括具有显着改善的电迁移电阻和/或抗应力迁移电阻的金属互连。铜互连107包括硅 - 下部浓度区域104和设置在其上的硅固溶体层106。硅固溶层106具有这样的结构，其中将硅原子引入构成铜互连件107的晶格结构内，作为晶间点原子或取代原子被布置在晶格内。硅固溶层106具有其中保留铜（面心立方晶格;晶格常数为3.6埃）的晶格结构，而硅原子被引入作为晶间点原子或取代原子的结构。

10. 发明申请

US20060214300A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060214300A1
公开(公告)日：2006-09-28
申请号：US11369955
申请日：2006-03-08
申请人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
发明人： Kenichi Yamamoto , Masashige Moritoki , Takashi Shimane , Kazumi Saito , Hiroaki Tomimori , Takamasa Itou , Kousei Ushijima , Katsuro Tateyama
IPC分类号： H01L23/52
CPC分类号： H01L21/02063 , H01L21/76814
摘要： An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.
摘要翻译：由于可以有效地防止在形成通孔之后形成和生长的改变层的存在而导致的通孔电阻的增加，从而提供了半导体器件的改进的可靠性。一种方法包括：在半导体衬底上形成TiN膜; 在TiN膜的表面上形成层间绝缘膜; 在所述层间绝缘膜的表面上形成抗蚀剂膜; 蚀刻其上形成有抗蚀剂膜的半导体衬底以形成开口，从而部分地暴露TiN膜; 等离子体处理TiN膜的暴露部分以去除在TiN膜的暴露部分中形成的改变的层; 并通过高温等离子体处理剥离抗蚀剂膜。

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