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    • 1. 发明授权
    • Memory control unit and memory control method and medium containing program for realizing the same
    • 存储器控制单元和存储器控制方法以及包含用于实现该程序的介质
    • US06340973B1
    • 2002-01-22
    • US09244036
    • 1999-02-04
    • Toshiyuki OchiaiYosuke FurukawaYutaka TanakaKozo KimuraMakoto HiraiTokuzo KiyoharaHideshi Nishida
    • Toshiyuki OchiaiYosuke FurukawaYutaka TanakaKozo KimuraMakoto HiraiTokuzo KiyoharaHideshi Nishida
    • G06F13372
    • G06F13/1647G11C7/1072G11C7/22
    • A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.
    • 传输目标单元输出用于数据读取和数据写入的命令。 地址生成器根据命令生成控制信号,并输出通过读取访问首先传送的数据的字节数。 命令发生器根据控制信号产生控制命令以控制SDRAM。 此时,命令生成器判断要进行控制的传送字节数,使得SDRAM从数据传输中最有效的指令按顺序执行指令。 也就是说,在通过存储体边界读取数据的情况下,命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个,以控制SDRAM。 数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式,可以发出命令,以便在数据读取的情况下以最小数量的周期终止数据传输 不断对不同的银行进行处理。 因此可以减少两次连续访问(对存储体0和存储体1的访问)所需的周期数,从而增加SDRAM的有效传输速率。
    • 2. 发明授权
    • Data transfer system which divides data among transfer units having
different transfer speed characteristics
    • 数据传输系统,其在具有不同传送速度特性的传送单元之间划分数据
    • US6141729A
    • 2000-10-31
    • US723872
    • 1996-09-23
    • Hideo IshidaToshiyuki OchiaiYutaka TanakaTeruto HirotaAkihiko WadaEiichi ToyonagaKunihiko Sakoda
    • Hideo IshidaToshiyuki OchiaiYutaka TanakaTeruto HirotaAkihiko WadaEiichi ToyonagaKunihiko Sakoda
    • G06F12/00G06F13/00G06F13/38G06F15/173G06F12/02
    • G06F13/387
    • A data transfer system comprises a plurality of terminals; a plurality of high-speed data transfer units connected to the terminals through a network, each data transfer unit comprising a plurality of storage devices and a storage device group control device or unit for controlling readout of data from the storage devices, and dividing and storing data requested by the terminals; a virtual storage device group controlling device or unit for controlling readout of data from virtual storage device groups, each virtual storage device group being constructed by selecting a storage device from each high-speed data transfer unit; and an instruction conversion unit or device for receiving a data readout instruction on the basis of data requests output from the terminals, which instruction is given to the virtual storage device groups, from the virtual storage device group control unit or device, and converting the instruction into a data readout instruction to the storage devices from the storage device group control unit or device. In this data transfer system, the load for the data transfer processing is equally distributed among the high-speed data transfer units even when data transfer requests are output from plural terminals.
    • 数据传输系统包括多个终端; 通过网络连接到终端的多个高速数据传送单元,每个数据传送单元包括多个存储设备和用于控制来自存储设备的数据读出的存储设备组控制设备或单元,以及分配和存储 终端请求的数据; 虚拟存储设备组控制设备或单元,用于控制来自虚拟存储设备组的数据读取,每个虚拟存储设备组通过从每个高速数据传送单元中选择一个存储设备来构造; 以及指令转换单元或装置,用于基于从虚拟存储设备组控制单元或设备向虚拟存储设备组发送指令,从终端输出的数据请求接收数据读出指令,并将指令转换 从存储设备组控制单元或设备到存储设备的数据读取指令。 在该数据传送系统中,即使当从多个终端输出数据传送请求时,数据传送处理的负载也均匀地分配在高速数据传送单元中。
    • 4. 发明申请
    • GLOW PLUG CONTROL DRIVE METHOD AND GLOW PLUG DRIVE CONTROL SYSTEM
    • GLOW插头控制驱动方法和GLOW PLUG驱动控制系统
    • US20130255615A1
    • 2013-10-03
    • US13993165
    • 2011-12-06
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • F02P23/00
    • F02P23/00F02D2041/2027F02P19/02F02P19/022F02P19/023F02P19/026F23Q7/001
    • To suppress current fluctuations upon commencement of driving and prolong lifespan by reducing electric stress caused by current fluctuations.A glow plug 1, a glow switch 2, and a stabilizing coil 3 are series-connected, and upon commencement of the driving of the glow plug 1, a repetition frequency of PWM signals that control the opening and closing of the glow switch 2 is made into a higher frequency than a repetition frequency in a normal drive state and the opening and closing of the glow switch 2 is controlled (S104), and when a predetermined drive shift condition has been met (S106), the repetition frequency of the PWM signals is returned to the frequency during normal driving and the opening and closing of the glow switch 2 is controlled (S108), whereby the current upon commencement of driving is smoothed and the occurrence of an instantaneous large current is suppressed.
    • 为了抑制驱动开始时的电流波动,通过减少由电流波动引起的电应力来延长寿命。 电热塞1,辉光开关2和稳定线圈3是串联的,并且在电热塞1的驱动开始时,控制辉光开关2的打开和关闭的PWM信号的重复频率是 在正常驱动状态下被制成比重复频率高的频率,并且控制辉光开关2的打开和关闭(S104),并且当满足预定的驱动移位条件(S106)时,PWM的重复频率 信号在正常驱动期间返回到频率,并且控制辉光开关2的打开和关闭(S108),从而驱动开始时的电流平滑,并且抑制了瞬时大电流的发生。
    • 5. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08159852B2
    • 2012-04-17
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。
    • 6. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20090268499A1
    • 2009-10-29
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02G11C5/06G11C8/16
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。
    • 10. 发明授权
    • Shield case for electronic apparatus
    • 电子设备屏蔽箱
    • US06977822B2
    • 2005-12-20
    • US10336092
    • 2003-01-03
    • Koji OtaniYutaka Tanaka
    • Koji OtaniYutaka Tanaka
    • H05K9/00H05K7/14
    • H05K9/0016H05K9/0018
    • The position of a connector 36 in the forward direction (Ya direction) is determined by having front end surfaces 36f1, 36g1 of protrusions 36f, 36g of the connector that protrude from the left side surface and the right side surface of the connector, respectively, contacting vertical wall portions 72a1, 74a1 of positioning concave portions 72a, 74a of supporting plates 72, 74 of a housing of the shield case. The position of the connector in the backward direction (Yb direction) is determined by having a back surface 36h of the connector 36 contacting a protrusion 70a of a dividing plate 70. The motion of the connector in the right-and-left directions (Xa-Xb directions) is controlled by having the left side surface and the right side surface of the connector facing the supporting plates, respectively, in close proximity. Since the connector is held in a status where no shaking occurs in any direction, there is no need to be sensitive about the assembling accuracy of the portion of the stereo device corresponding to the position of the electronic apparatus, and thus more freedom for back surface panel configuration of the stereo devices can be provided and this reduces the burden of the manufacturers when manufacturing the stereo devices.
    • 连接器36在正向(Ya方向)上的位置由前端面36f 1,36g 1的突起36f,连接器的从左侧面突出的36g和右侧面 分别与屏蔽壳体的壳体的支撑板72,74的定位凹部72a,74a的垂直壁部72a,1,7aa1接触。 连接器在向后方向(Yb方向)上的位置由连接器36的后表面36h接触分隔板70的突出部70a来确定。 连接器的左右方向(Xa-Xb方向)的运动分别通过使连接器的左侧表面和右侧表面分别靠近支撑板来控制。 由于连接器保持在任何方向上不发生振动的状态,因此对于与电子设备的位置相对应的立体声装置的部分的组装精度不需要敏感,因此对于背面的自由度更高 可以提供立体声装置的面板配置,并且这减少了制造立体声装置时制造商的负担。