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1. 发明授权

US08630106B2 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate 有权
标题翻译：具有各自包括电荷累积层和控制栅极的存储单元的半导体存储器件
公开(公告)号：US08630106B2
公开(公告)日：2014-01-14
申请号：US12695623
申请日：2010-01-28
申请人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
发明人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M
摘要翻译：半导体存储器件包括存储单元单元，字线，驱动电路和第一晶体管。字线连接到第0至第N个存储单元的控制栅极。第（N + 1）个第一晶体管的数量分别将电压转移到字线。将电压转移到第i个（i是0到N的范围内的自然数）字线的第一晶体管中的一个以上，靠近第i个字线的字线的M（M

2. 发明申请

US20120275226A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION 审中-公开
标题翻译：可降低功耗的非易失性半导体存储器件
公开(公告)号：US20120275226A1
公开(公告)日：2012-11-01
申请号：US13428384
申请日：2012-03-23
申请人： Dai Nakamura , Takatoshi Minamoto , Junji Musha , Mai Muramoro
发明人： Dai Nakamura , Takatoshi Minamoto , Junji Musha , Mai Muramoro
IPC分类号： G11C16/28 , G11C16/04 , G11C16/26
CPC分类号： G11C5/14 , G11C16/10 , G11C16/26 , G11C16/30
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supply is supplied to the first power supply pad. A second power supply, a voltage of which is higher than that of the first power supply is supplied to the second power supply pad. The voltage reduction circuit reduces the second power supply, generates a first voltage lower than that of the second power supply, and supplies the first voltage to the nonvolatile memory. The first pump circuit generates a voltage higher than that of the second power supply on the basis of the first power supply, and supplies the second voltage to the nonvolatile memory.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括电可重写非易失性存储器，接地焊盘，第一电源焊盘，第二电源焊盘，降压电路和第一泵电路。第一电源被提供给第一电源板。其电压高于第一电源的第二电源被提供给第二电源焊盘。电压降低电路减少第二电源，产生低于第二电源的第一电压，并将第一电压提供给非易失性存储器。第一泵电路基于第一电源产生比第二电源的电压高的电压，并将第二电压提供给非易失性存储器。

3. 发明授权

US08659968B2 Power supply circuit and semiconductor memory device including the power supply circuit 失效
标题翻译：电源电路和包括电源电路的半导体存储器件
公开(公告)号：US08659968B2
公开(公告)日：2014-02-25
申请号：US13178823
申请日：2011-07-08
申请人： Takatoshi Minamoto
发明人： Takatoshi Minamoto
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/147 , G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： According to one embodiment, a power supply circuit, which generates a power supply voltage which is applied to a memory cell array including a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines, comprises a first boost circuit configured to boost an input voltage, a first voltage step-down circuit having an input connected to an output of the first boost circuit, and a voltage control circuit configured to control the first boost circuit and the first voltage step-down circuit. The voltage control circuit is configured to generate, not via the first voltage step-down circuit, a voltage which is boosted by the first boost circuit, when a first voltage is transferred to a non-selected memory cell.
摘要翻译：根据一个实施例，产生施加到存储单元阵列的电源电压的电源电路包括设置在多个字线和多个位线之间的交叉处的多个存储单元，包括第一升压被配置为升高输入电压的电路，具有连接到第一升压电路的输出的输入的第一降压电路以及被配置为控制第一升压电路和第一降压电路的电压控制电路。电压控制电路被配置为当第一电压被传送到未选择的存储单元时，不经由第一降压电路产生由第一升压电路升压的电压。

4. 发明申请

US20120306570A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20120306570A1
公开(公告)日：2012-12-06
申请号：US13323040
申请日：2011-12-12
申请人： Mai MURAMOTO , Takatoshi Minamoto
发明人： Mai MURAMOTO , Takatoshi Minamoto
IPC分类号： H01L25/00
CPC分类号： H03K17/063 , H01L21/28273 , H01L23/5222 , H01L23/5225 , H01L27/0207 , H01L27/0222 , H01L27/0629 , H01L28/60 , H01L29/42324 , H01L29/788 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.
摘要翻译：根据实施例的半导体集成电路包括转移晶体管，其包括第一栅电极，第一栅电极和与第一布线二极管连接的扩散层，以及至少提供时钟信号的时钟信号线作为时钟信号线的一部分的第一部分时钟信号线的一部分形成在第一栅电极的上方。

5. 发明授权

US08779844B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08779844B2
公开(公告)日：2014-07-15
申请号：US13323040
申请日：2011-12-12
申请人： Mai Muramoto , Takatoshi Minamoto
发明人： Mai Muramoto , Takatoshi Minamoto
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/063 , H01L21/28273 , H01L23/5222 , H01L23/5225 , H01L27/0207 , H01L27/0222 , H01L27/0629 , H01L28/60 , H01L29/42324 , H01L29/788 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.
摘要翻译：根据实施例的半导体集成电路包括转移晶体管，其包括第一栅电极，第一栅电极和与第一布线二极管连接的扩散层，以及至少提供时钟信号的时钟信号线作为时钟信号线的一部分的第一部分时钟信号线的一部分形成在第一栅电极的上方。

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