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1. 发明授权

US09129688B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US09129688B2
公开(公告)日：2015-09-08
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/16 , G11C16/04 , H01L27/115
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

2. 发明申请

US20130003461A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE 有权
标题翻译：可减少芯片尺寸的半导体存储器件
公开(公告)号：US20130003461A1
公开(公告)日：2013-01-03
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki ISOBE , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki ISOBE , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

3. 发明授权

US08295090B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US08295090B2
公开(公告)日：2012-10-23
申请号：US12817697
申请日：2010-06-17
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

4. 发明申请

US20110134695A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110134695A1
公开(公告)日：2011-06-09
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

5. 发明授权

US08315094B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08315094B2
公开(公告)日：2012-11-20
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

6. 发明授权

US08274826B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US08274826B2
公开(公告)日：2012-09-25
申请号：US12838867
申请日：2010-07-19
申请人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
发明人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
IPC分类号： G11C16/04
CPC分类号： G11C16/06
摘要： According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.
摘要翻译：根据一个实施例，NAND型闪速存储器包括设置在第一和第二存储器平面之间的第一传输晶体管，第一传输晶体管的第一电位传输端共同连接到第一NAND块中的第一字线，第二字配置在第三NAND块中的第二转移晶体管，设置在第一存储器平面的第一端的第二转移晶体管，第二转移晶体管的第一电位转移端连接到第二NAND块中的第三字线，以及第三转移晶体管设置在第二存储器平面的第二端，第三传输晶体管的第一电位传输端连接到第四NAND块中的第四字线。

7. 发明申请

US20110019477A1 NAND TYPE FLASH MEMORY 有权
标题翻译： NAND型闪存
公开(公告)号：US20110019477A1
公开(公告)日：2011-01-27
申请号：US12838867
申请日：2010-07-19
申请人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
发明人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
IPC分类号： G11C16/04
CPC分类号： G11C16/06
摘要： According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.
摘要翻译：根据一个实施例，NAND型闪速存储器包括设置在第一和第二存储器平面之间的第一传输晶体管，第一传输晶体管的第一电位传输端共同连接到第一NAND块中的第一字线，第二字配置在第三NAND块中的第二转移晶体管，设置在第一存储器平面的第一端的第二转移晶体管，第二转移晶体管的第一电位转移端连接到第二NAND块中的第三字线，以及第三转移晶体管设置在第二存储器平面的第二端，第三传输晶体管的第一电位传输端连接到第四NAND块中的第四字线。

8. 发明授权

US08630106B2 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate 有权
标题翻译：具有各自包括电荷累积层和控制栅极的存储单元的半导体存储器件
公开(公告)号：US08630106B2
公开(公告)日：2014-01-14
申请号：US12695623
申请日：2010-01-28
申请人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
发明人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M
摘要翻译：半导体存储器件包括存储单元单元，字线，驱动电路和第一晶体管。字线连接到第0至第N个存储单元的控制栅极。第（N + 1）个第一晶体管的数量分别将电压转移到字线。将电压转移到第i个（i是0到N的范围内的自然数）字线的第一晶体管中的一个以上，靠近第i个字线的字线的M（M

9. 发明授权

US08243491B2 Semiconductor integrated circuit including semiconductor memory 失效
标题翻译：半导体集成电路包括半导体存储器
公开(公告)号：US08243491B2
公开(公告)日：2012-08-14
申请号：US12884378
申请日：2010-09-17
申请人： Toshiki Hisada , Hiromitsu Mashita
发明人： Toshiki Hisada , Hiromitsu Mashita
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C7/18 , G11C2207/002 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.
摘要翻译：根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。位线包括顺序排列的第一，第二，第三和第四位线。第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。

10. 发明申请

US20120001331A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120001331A1
公开(公告)日：2012-01-05
申请号：US13051652
申请日：2011-03-18
申请人： Takayuki Toba , Tohru Ozaki , Toshiki Hisada , Hiromitsu Mashita , Takafumi Taguchi
发明人： Takayuki Toba , Tohru Ozaki , Toshiki Hisada , Hiromitsu Mashita , Takafumi Taguchi
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L21/76816 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.
摘要翻译：根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。多个第一互连周期性地布置成在一个方向上延伸。第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。第三互连设置在组和第二互连之间。多个导电构件设置在从第二互连件观察的与组相反的一侧上。第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

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