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1. 发明授权

US07585614B2 Sub-lithographic imaging techniques and processes 失效
标题翻译：亚光刻成像技术和工艺
公开(公告)号：US07585614B2
公开(公告)日：2009-09-08
申请号：US10711458
申请日：2004-09-20
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.
摘要翻译：提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。另一个边缘被记住在图层中。去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

2. 发明授权

US06875685B1 Method of forming gas dielectric with support structure 失效
标题翻译：用支撑结构形成气体电介质的方法
公开(公告)号：US06875685B1
公开(公告)日：2005-04-05
申请号：US10605766
申请日：2003-10-24
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.
摘要翻译：在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。在翼层电介质中形成诸如通孔或互连的导电结构。然后形成连接到导电结构的支撑件，支撑件包括其下的区域。然后从该区域去除布线层电介质以形成气体电介质。

3. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

4. 发明授权

US06417515B1 In-situ ion implant activation and measurement apparatus 有权
标题翻译：原位离子注入激活和测量装置
公开(公告)号：US06417515B1
公开(公告)日：2002-07-09
申请号：US09527192
申请日：2000-03-17
申请人： Howard T. Barrett , John J. Ellis-Monaghan , Toshiharu Furukawa , James A. Slinkman
发明人： Howard T. Barrett , John J. Ellis-Monaghan , Toshiharu Furukawa , James A. Slinkman
IPC分类号： H01J37317
CPC分类号： H01J37/3171 , H01J2237/30466 , H01J2237/31703
摘要： A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.
摘要翻译：将衬底（例如半导体芯片或晶片）与产品晶片一起植入离子注入真空系统中。然后在基板处于真空系统内的退火步骤中退火基板。退火炉是快速热退火炉，例如激光退火炉或闪光灯退火炉。退火步骤不影响产品晶圆。然后对植入和退火的基底进行测量，同时它在可以适当地与植入剂量相关联的真空系统内。该测量可以采用诸如四点探针的技术或者用来测量从植入的衬底的表面的光学反射率的工具。如果需要，可以将另外的植入物提供给产品晶片以更接近所需剂量。

5. 发明授权

US06274465B1 DC electric field assisted anneal 失效
标题翻译：直流电场辅助退火
公开(公告)号：US06274465B1
公开(公告)日：2001-08-14
申请号：US09538309
申请日：2000-03-30
申请人： Arne W. Ballantine , John J. Ellis-Monaghan , Toshiharu Furukawa , Glenn R. Miller , James A. Slinkman
发明人： Arne W. Ballantine , John J. Ellis-Monaghan , Toshiharu Furukawa , Glenn R. Miller , James A. Slinkman
IPC分类号： H01L2104
CPC分类号： H01L21/324 , H01L21/2253 , H01L21/26513 , H01L21/326
摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.
摘要翻译：一种用于在半导体器件中形成期望的接合剖面的方法。将至少一种掺杂剂引入到半导体衬底中。所述至少一种掺杂剂通过半导体衬底和所述至少一种掺杂剂退火而在半导体衬底中扩散，同时将半导体衬底暴露于DC电场。

6. 发明申请

US20130134518A1 NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：半导体绝缘体基板的顶层硅层中的气体植入区域
公开(公告)号：US20130134518A1
公开(公告)日：2013-05-30
申请号：US13280681
申请日：2011-11-28
申请人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , William F. Clark, JR. , Richard A. Phelps , BethAnn Rainey , Yun Shi , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L21/84 , H01L27/1203
摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
摘要翻译：半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

7. 发明申请

US20100117122A1 Optimized Device Isolation 有权
标题翻译：优化设备隔离
公开(公告)号：US20100117122A1
公开(公告)日：2010-05-13
申请号：US12269073
申请日：2008-11-12
申请人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St Onge , James A. Slinkman
发明人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St Onge , James A. Slinkman
IPC分类号： H01L27/092 , H01L27/085
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.
摘要翻译：用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域上方，并在所有p阱区域下方， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。隔离MOSFET的n阱连接到深n波段区域。所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

8. 发明授权

US07479688B2 STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权
标题翻译：通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能
公开(公告)号：US07479688B2
公开(公告)日：2009-01-20
申请号：US10751831
申请日：2004-01-05
申请人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
发明人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
IPC分类号： H01L29/72
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译：一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。在又一实施例中，等离子体氮化处理发生在沟槽填充之后。在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

9. 发明申请

US20080157077A1 Integrated Circuit and Methods of Measurement And Preparation of Measurement Structure 失效
标题翻译：集成电路和测量结构的制备方法
公开(公告)号：US20080157077A1
公开(公告)日：2008-07-03
申请号：US12044030
申请日：2008-03-07
申请人： G. W. Banke , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
发明人： G. W. Banke , Andrew Deering , Philip V. Kaszuba , Leon Moszkowicz , James Robert , James A. Slinkman
IPC分类号： H01L21/66
CPC分类号： A61M1/0058 , A61M1/0084 , G01N1/32 , G01R31/2898
摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
摘要翻译：通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。然后可以使用原子力显微镜（AFM）对印记进行成像。该图像可用于测量结构的底面。

10. 发明申请

US20080131795A1 METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS 有权
标题翻译：使用热诱导油脂应力调整光刻掩模的方法
公开(公告)号：US20080131795A1
公开(公告)日：2008-06-05
申请号：US12029506
申请日：2008-02-12
申请人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistron
发明人： Emily F. Gallagher , Louis M. Kindt , James A. Slinkman , Richard E. Wistron
IPC分类号： G03F1/00
CPC分类号： G03F1/64 , G03F1/60
摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature, and the pellicle frame is mounted to the mask at the mounting temperature.
摘要翻译：调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度，安装温度对应于施加的应力。防护薄膜组件框架的实际温度被调整到确定的安装温度，并且防护膜框架在安装温度下安装到掩模上。

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