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    • 3. 发明授权
    • Programmable read only memory
    • 可编程只读存储器
    • US4404659A
    • 1983-09-13
    • US193411
    • 1980-10-03
    • Toshimasa KiharaToshifumi Inoue
    • Toshimasa KiharaToshifumi Inoue
    • G11C17/00G11C16/06G11C16/10G11C16/32G11C11/40
    • G11C16/10G11C16/32
    • A programmable read only memory consists of a plurality of FAMOS's having a control gate. Control gates of the plurality of FAMOS's arrayed along the same row are commonly connected to a word line, and drains of the plurality of FAMOS's arrayed along the same column are commonly connected to a bit line. Sources of the plurality of FAMOS's are commonly connected, and are connected to a ground point of the circuit via resistance means. Bit lines which are selected when the data is to be written are provided with a high voltage. Floating gates of the non-selected FAMOS's are coupled by parasitic capacity which exists between the floating gate and the drain. Therefore, when the voltage of the bit line is raised, the voltage of the floating gate is undesirably raised correspondingly. In this case, however, voltage drops across said resistance means owing to the writing current which flows through the selected FAMOS, and the potential of the commonly connected sources is raised by the drop in the voltage. Consequently, the non-selected FAMOS's are properly maintained in the non-conductive state despite the fact that the potential of the floating gate is raised as mentioned above.
    • 可编程只读存储器由具有控制门的多个FAMOS组成。 沿着同一行排列的多个FAMOS的控制栅极通常连接到字线,并且沿同一列排列的多个FAMOS的漏极通常连接到位线。 多个FAMOS的源极共同连接,并且通过电阻装置连接到电路的接地点。 当要写入数据时选择的位线被提供高电压。 未选择的FAMOS的浮动栅极通过存在于浮动栅极和漏极之间的寄生电容耦合。 因此,当位线的电压升高时,浮栅的电压相应地不期望地升高。 然而,在这种情况下,由于流过所选择的FAMOS的写入电流,所述电阻装置的电压下降,并且共同连接的电源的电位由于电压的下降而升高。 因此,尽管浮动栅极的电位如上所述地升高,但是未选择的FAMOS被适当地保持在非导通状态。
    • 6. 发明授权
    • Method of and apparatus for compressing image data
    • 压缩图像数据的方法和装置
    • US4764975A
    • 1988-08-16
    • US897760
    • 1986-08-05
    • Toshifumi Inoue
    • Toshifumi Inoue
    • G06F3/14G06T3/40G09G5/36H04N1/393G06K9/36
    • G06T3/40H04N1/3935
    • The present invention relates to image data compression utilized either when an original image is displayed on a monitor or when an original is reproduced with a desired reduction ratio. Pixel data of an original image are sequentially inputted synchronously with a clock signal (CY), and an average value of pixel data inputted theretofore is renewed in an averaging circuit (40) each time pixel data are inputted. The renewal of the average value is repeated until an assignment signal (CX) is outputted from a DDA circuit (30). The assignment signal assigns pixels of the original image to the same number of blocks as the number of pixels of a desired compressed image, which is adapted for a desired image compression. An output obtained from the averaging circuit (40) represents an average value of pixel data with respect to each block aligned in the vertical direction of the original image. In a DDA circuit (50) an assignment for blocks in the horizontal direction of the original is carried out. Average values of pixel data with respect to each block adaptable for the desired image compression are obtained by an averaging circuit ( 60), which average values are used as pixel data of each pixel of the compression image.
    • PCT No.PCT / JP85 / 00671 Sec。 371日期:1986年8月5日 102(e)日期1986年8月5日PCT提交1985年12月6日PCT公布。 出版物WO86 / 03610 日期:1986年6月19日。本发明涉及当在监视器上显示原始图像时或当以期望的缩小比率再现原件时所使用的图像数据压缩。 原始图像的像素数据与时钟信号(CY)同步地顺序地输入,并且每当输入像素数据时,在平均电路(40)中更新输入的像素数据的平均值。 重复平均值的更新,直到从DDA电路(30)输出分配信号(CX)。 分配信号将原始图像的像素分配给与适合于期望的图像压缩的期望压缩图像的像素数相同的块数。 从平均电路(40)获得的输出表示相对于在原始图像的垂直方向上排列的每个块的像素数据的平均值。 在DDA电路(50)中,执行原稿的水平方向上的块的分配。 通过平均电路(60)获得相对于适用于期望图像压缩的每个块的像素数据的平均值,该平均值被用作压缩图像的每个像素的像素数据。