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    • 5. 发明授权
    • Time-sharing data transfer apparatus
    • 分时数据传输设备
    • US5280482A
    • 1994-01-18
    • US896635
    • 1992-06-10
    • Hideaki KitamuraToshifumi Inoue
    • Hideaki KitamuraToshifumi Inoue
    • G06F13/36G06F13/362G06F13/372H04L12/40
    • G06F13/3625
    • An apparatus for transferring data in a time-sharing mode includes a plurality of modules connected to a common bus line for transferring data therethrough, a bus controller for controlling a time-sharing transfer of data between the modules, and a system controller connected to the modules and bus controller through a bidirectional command line. The system controller is operable, upon receipt of a data transfer request or data transfer completion notice from certain of the modules, to command the bus controller to generate or eliminate a bus slot. Then, the bus controller sets a new bus slot to a bus cycle, or eliminates a designated slot from the bus cycle, thereby to vary the number of slots constituting the bus cycle. Slot enable signals corresponding to the respective slots are transmitted to the modules through the bus line. Each module successively compares a slot number and slot enable signals, and exchanges data with the bus line upon agreement between the slot number and slot enable signals.
    • 用于以分时模式传送数据的装置包括连接到用于传送数据的公共总线的多个模块,用于控制模块之间的数据分时传输的总线控制器和连接到该模块的系统控制器 模块和总线控制器通过双向命令行。 系统控制器在接收到来自某些模块的数据传输请求或数据传送完成通知时可操作,命令总线控制器产生或消除总线插槽。 然后,总线控制器将总线时隙设置为总线周期,或者从总线周期中消除指定的时隙,从而改变构成总线周期的时隙数。 通过总线将对应于各个时隙的时隙使能信号发送到模块。 每个模块连续地比较时隙号和时隙使能信号,并且在时隙号和时隙使能信号之间一致地与总线交换数据。
    • 7. 发明授权
    • Programmable read only memory
    • 可编程只读存储器
    • US4404659A
    • 1983-09-13
    • US193411
    • 1980-10-03
    • Toshimasa KiharaToshifumi Inoue
    • Toshimasa KiharaToshifumi Inoue
    • G11C17/00G11C16/06G11C16/10G11C16/32G11C11/40
    • G11C16/10G11C16/32
    • A programmable read only memory consists of a plurality of FAMOS's having a control gate. Control gates of the plurality of FAMOS's arrayed along the same row are commonly connected to a word line, and drains of the plurality of FAMOS's arrayed along the same column are commonly connected to a bit line. Sources of the plurality of FAMOS's are commonly connected, and are connected to a ground point of the circuit via resistance means. Bit lines which are selected when the data is to be written are provided with a high voltage. Floating gates of the non-selected FAMOS's are coupled by parasitic capacity which exists between the floating gate and the drain. Therefore, when the voltage of the bit line is raised, the voltage of the floating gate is undesirably raised correspondingly. In this case, however, voltage drops across said resistance means owing to the writing current which flows through the selected FAMOS, and the potential of the commonly connected sources is raised by the drop in the voltage. Consequently, the non-selected FAMOS's are properly maintained in the non-conductive state despite the fact that the potential of the floating gate is raised as mentioned above.
    • 可编程只读存储器由具有控制门的多个FAMOS组成。 沿着同一行排列的多个FAMOS的控制栅极通常连接到字线,并且沿同一列排列的多个FAMOS的漏极通常连接到位线。 多个FAMOS的源极共同连接,并且通过电阻装置连接到电路的接地点。 当要写入数据时选择的位线被提供高电压。 未选择的FAMOS的浮动栅极通过存在于浮动栅极和漏极之间的寄生电容耦合。 因此,当位线的电压升高时,浮栅的电压相应地不期望地升高。 然而,在这种情况下,由于流过所选择的FAMOS的写入电流,所述电阻装置的电压下降,并且共同连接的电源的电位由于电压的下降而升高。 因此,尽管浮动栅极的电位如上所述地升高,但是未选择的FAMOS被适当地保持在非导通状态。