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1. 发明授权

US06194759B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06194759B1
公开(公告)日：2001-02-27
申请号：US09436225
申请日：1999-11-09
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , G11C2216/08 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

2. 发明授权

US6040605A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6040605A
公开(公告)日：2000-03-21
申请号：US236630
申请日：1999-01-26
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888 , G11C2216/08
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

3. 再颁专利

USRE41868E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41868E1
公开(公告)日：2010-10-26
申请号：US11708145
申请日：2007-02-20
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , G11C2216/08 , H01L21/28273 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888 , H01L29/7889
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

4. 发明授权

US07375399B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07375399B2
公开(公告)日：2008-05-20
申请号：US11156558
申请日：2005-06-21
申请人： Tomoyuki Ishii , Toshiyuki Mine , Toshiaki Sano , Norifumi Kameshiro
发明人： Tomoyuki Ishii , Toshiyuki Mine , Toshiaki Sano , Norifumi Kameshiro
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , G11C11/405 , G11C2207/104 , H01L21/823456 , H01L21/823462 , H01L27/1052 , H01L27/11 , H01L27/1116
摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.
摘要翻译：本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

5. 发明授权

US08106449B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08106449B2
公开(公告)日：2012-01-31
申请号：US11493688
申请日：2006-07-27
申请人： Toshiaki Sano , Tomoyuki Ishii , Norifumi Kameshiro , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Norifumi Kameshiro , Toshiyuki Mine
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11 , H01L27/11517 , H01L27/1203 , H01L29/41783 , H01L29/78
摘要： To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.
摘要翻译：为了在具有增益单元结构的存储单元中实现稳定的读取操作，构造了写入晶体管，其具有形成在绝缘层上的源极和漏极，形成在绝缘层上并且在源极和所述漏极由半导体构成，栅极形成在所述绝缘层的上部，所述源极与漏极之间，并且通过栅极绝缘膜与所述沟道电绝缘并控制所述沟道的电位。通道将源极和漏极的侧表面上的源极和漏极电连接。

6. 发明授权

US5684734A Semiconductor element and process for manufacturing the same 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US5684734A
公开(公告)日：1997-11-04
申请号：US600678
申请日：1996-02-13
申请人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
发明人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
IPC分类号： H01L27/115 , H01L27/12 , H01L29/68 , H01L29/788 , G11C17/00
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/1203 , H01L29/685 , H01L29/7883 , Y10S438/962
摘要： A semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against the noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size.
摘要翻译：公开了一种半导体存储元件，其可以在多个存储元件中容易地共享端子，并且可以通过高电流并且抵抗噪声。为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。因此，该元件可以具有小尺寸并且可以高密度地存储信息。因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。

7. 发明申请

US20080261357A1 METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20080261357A1
公开(公告)日：2008-10-23
申请号：US11956858
申请日：2007-12-14
申请人： Norifumi KAMESHIRO , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
发明人： Norifumi KAMESHIRO , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L29/66613 , H01L29/66772
摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.
摘要翻译：在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。然后，在源极 - 漏极材料膜上形成掩模层。接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

8. 发明授权

US07772053B2 Method for fabrication of semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07772053B2
公开(公告)日：2010-08-10
申请号：US11956858
申请日：2007-12-14
申请人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
发明人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/66613 , H01L29/66772
摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.
摘要翻译：在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。然后，在源极 - 漏极材料膜上形成掩模层。接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

9. 发明授权

US06876023B2 Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path 失效
标题翻译：具有从薄膜通道路径通过通道电流充电或放电的电荷累积区域的增益单元型非易失性存储器
公开(公告)号：US06876023B2
公开(公告)日：2005-04-05
申请号：US10158851
申请日：2002-06-03
申请人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/12 , H01L29/66 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/108 , H01L27/10873 , H01L27/12 , H01L27/1203 , H01L29/78642
摘要： A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.
摘要翻译：除了基于低泄漏电流或杂质注入以外的阈值电压控制方法的半导体存储元件。这样的半导体元件用于形成在缩小结构中使用的半导体存储器元件，并且由于足够长的刷新周期而有利于高速写入操作。这些半导体存储元件又用于构成半导体存储器件。使用非常薄的半导体膜作为通道，使得通过膜厚度方向的量子力学容纳效应来降低泄漏电流。使用每个电荷累积区域中的电荷量来改变每个读取晶体管结构的源区和漏区之间的电导，所述电导变化用于数据存储。用于对每个电荷累积区进行充电或放电的晶体管的沟道由最多为5nm厚的半导体膜制成。该方案具有高速数据写入性能和扩展数据保留时间。本发明提供了高集成度的高速，省电的半导体器件，特别有利于生产低功耗的小规模系统。

10. 发明授权

US06337293B1 Method of forming a quantum memory element having a film of amorphous silicon 失效
标题翻译：形成具有非晶硅膜的量子存储元件的方法
公开(公告)号：US06337293B1
公开(公告)日：2002-01-08
申请号：US09332445
申请日：1999-06-14
申请人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
发明人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
IPC分类号： H01L2100
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/1203 , H01L29/685 , H01L29/7883 , Y10S438/962
摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.
摘要翻译：公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。因此，该元件可以具有小尺寸并且可以高密度地存储信息。因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。非晶硅层结晶成多晶硅膜。沉积半导体漏极以形成电荷捕获和存储区域。在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

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