专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080261357A1 METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20080261357A1
公开(公告)日：2008-10-23
申请号：US11956858
申请日：2007-12-14
申请人： Norifumi KAMESHIRO , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
发明人： Norifumi KAMESHIRO , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L29/66613 , H01L29/66772
摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.
摘要翻译：在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。然后，在源极 - 漏极材料膜上形成掩模层。接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

2. 发明申请

US20060227648A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060227648A1
公开(公告)日：2006-10-12
申请号：US11399397
申请日：2006-04-07
申请人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
发明人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C8/00
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

3. 发明授权

US07468901B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07468901B2
公开(公告)日：2008-12-23
申请号：US11399397
申请日：2006-04-07
申请人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
发明人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C7/00
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

4. 发明授权

US07375399B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07375399B2
公开(公告)日：2008-05-20
申请号：US11156558
申请日：2005-06-21
申请人： Tomoyuki Ishii , Toshiyuki Mine , Toshiaki Sano , Norifumi Kameshiro
发明人： Tomoyuki Ishii , Toshiyuki Mine , Toshiaki Sano , Norifumi Kameshiro
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , G11C11/405 , G11C2207/104 , H01L21/823456 , H01L21/823462 , H01L27/1052 , H01L27/11 , H01L27/1116
摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.
摘要翻译：本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

5. 发明申请

US20130140584A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130140584A1
公开(公告)日：2013-06-06
申请号：US13700729
申请日：2010-06-02
申请人： Norifumi Kameshiro , Natsuki Yokoyama
发明人： Norifumi Kameshiro , Natsuki Yokoyama
IPC分类号： H01L29/16
CPC分类号： H01L29/1608 , H01L21/8213 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p+) region. The JBS diode has a structure, which has an n region having a relatively high concentration compared with the n− drift layer concentration, said n region being in the lower portion of the junction barrier (p+) region.
摘要翻译：公开了一种JBS二极管，其中通过将电流充分地扩散到结屏障（p +）区域的下部来抑制导通电压的增加。 JBS二极管具有与n漂移层浓度相比具有相对高浓度的n区的结构，所述n区位于结屏障（p +）区域的下部。

6. 发明授权

US07772053B2 Method for fabrication of semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07772053B2
公开(公告)日：2010-08-10
申请号：US11956858
申请日：2007-12-14
申请人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
发明人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/66613 , H01L29/66772
摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.
摘要翻译：在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。然后，在源极 - 漏极材料膜上形成掩模层。接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

7. 发明申请

US20080285325A1 Semiconductor Memory Device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080285325A1
公开(公告)日：2008-11-20
申请号：US12186204
申请日：2008-08-05
申请人： NORIFUMI KAMESHIRO , Riichiro Takemura , Tomoyuki Ishii
发明人： NORIFUMI KAMESHIRO , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

8. 发明申请

US20130285071A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130285071A1
公开(公告)日：2013-10-31
申请号：US13883572
申请日：2010-11-08
申请人： Norifumi Kameshiro , Haruka Shimizu
发明人： Norifumi Kameshiro , Haruka Shimizu
IPC分类号： H01L29/16
CPC分类号： H01L29/1608 , H01L29/06 , H01L29/0615 , H01L29/0692 , H01L29/0843 , H01L29/0878 , H01L29/1095 , H01L29/12 , H01L29/47 , H01L29/6606 , H01L29/78 , H01L29/7811 , H01L29/80 , H01L29/808 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n−-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.
摘要翻译：在形成使用碳化硅的半导体器件的接合端接延伸结构的区域的前表面上形成具有浓度比n型漂移层的浓度高的n型半导体区域的结构。位于远离有源区域的一侧的连接终端延伸结构的边缘由其底表面到其前表面被n型半导体区域包围。通过这种方式，可以在确保耐压的同时提供具有低电阻的装置，或者通过降低装置的电阻，可以提供具有低功率损耗的装置。

9. 发明授权

US08106449B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08106449B2
公开(公告)日：2012-01-31
申请号：US11493688
申请日：2006-07-27
申请人： Toshiaki Sano , Tomoyuki Ishii , Norifumi Kameshiro , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Norifumi Kameshiro , Toshiyuki Mine
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11 , H01L27/11517 , H01L27/1203 , H01L29/41783 , H01L29/78
摘要： To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.
摘要翻译：为了在具有增益单元结构的存储单元中实现稳定的读取操作，构造了写入晶体管，其具有形成在绝缘层上的源极和漏极，形成在绝缘层上并且在源极和所述漏极由半导体构成，栅极形成在所述绝缘层的上部，所述源极与漏极之间，并且通过栅极绝缘膜与所述沟道电绝缘并控制所述沟道的电位。通道将源极和漏极的侧表面上的源极和漏极电连接。

10. 发明授权

US07859889B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07859889B2
公开(公告)日：2010-12-28
申请号：US12186204
申请日：2008-08-05
申请人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
发明人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式