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1. 发明授权

US4261004A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4261004A
公开(公告)日：1981-04-07
申请号：US929959
申请日：1978-08-01
申请人： Toshiaki Masuhara , Osamu Minato , Yoshio Sakai , Toshio Sasaki , Masaharu Kubo , Kotaro Nishimura , Tokumasa Yasui
发明人： Toshiaki Masuhara , Osamu Minato , Yoshio Sakai , Toshio Sasaki , Masaharu Kubo , Kotaro Nishimura , Tokumasa Yasui
IPC分类号： H03F1/52 , H01L21/02 , H01L21/822 , H01L23/62 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/08 , H01L29/78 , H03F1/42
CPC分类号： H01L28/20 , H01L27/0251 , H01L27/0288
摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..
摘要翻译：在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件，并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

2. 发明授权

US4199778A Interconnection structure for semiconductor integrated circuits 失效
标题翻译：半导体集成电路的互连结构
公开(公告)号：US4199778A
公开(公告)日：1980-04-22
申请号：US843366
申请日：1977-10-19
申请人： Toshiaki Masuhara , Tokumasa Yasui , Yoshio Sakai , Joh Nakajima , Yasunobu Kosa , Satoshi Meguro , Masaharu Kubo
发明人： Toshiaki Masuhara , Tokumasa Yasui , Yoshio Sakai , Joh Nakajima , Yasunobu Kosa , Satoshi Meguro , Masaharu Kubo
IPC分类号： H01L21/763 , H01L21/31 , H01L21/3205 , H01L21/3215 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/04 , H01L23/48 , H01L29/44
CPC分类号： H01L21/32155 , H01L21/76889 , H01L23/53271 , H01L2924/0002
摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.
摘要翻译：在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

3. 发明授权

US4507759A Static memory 失效
标题翻译：静态内存
公开(公告)号：US4507759A
公开(公告)日：1985-03-26
申请号：US343590
申请日：1982-01-28
申请人： Tokumasa Yasui , Hideaki Nakamura , Kiyofumi Uchibori , Nobuyoshi Tanimura , Osamu Minato
发明人： Tokumasa Yasui , Hideaki Nakamura , Kiyofumi Uchibori , Nobuyoshi Tanimura , Osamu Minato
IPC分类号： G11C11/417 , G11C11/409 , G11C11/419 , H01L27/11 , G11C7/02
CPC分类号： G11C11/419 , H01L27/1112
摘要： In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.
摘要翻译：在MOS静态RAM中，配置在存储器阵列中的数据线和通过数据线选择电路与数据线耦合的公共数据线通过偏压MOSFET提供低于电源电压电平的偏置电压。通常，在RAM的待机时间长的情况下，数据线和公共数据线的偏置电压由偏置MOSFET的漏电流或拖尾电流异常升高。结果，RAM的数据读出速度降低。通过在相应数据线和公共数据线之间连接电阻较高的电阻（例如由多晶硅层制成）的电阻元件和电路的接地点来防止数据线和公共数据线的这种异常电位增加。

4. 发明授权

US5446689A Semiconductor memory having a polycrystalline silicon load resistor and CMOS peripheral circuitry 失效
标题翻译：具有多晶硅负载电阻器和CMOS外围电路的半导体存储器
公开(公告)号：US5446689A
公开(公告)日：1995-08-29
申请号：US230814
申请日：1994-04-21
申请人： Tokumasa Yasui , Shinji Shimizu , Kotaro Nishimura
发明人： Tokumasa Yasui , Shinji Shimizu , Kotaro Nishimura
IPC分类号： G11C11/412 , G11C11/418 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/11 , H03K19/0185 , G11C11/417
CPC分类号： G11C11/412 , G11C11/418 , H01L27/0688 , H01L27/0927 , H01L27/1112 , H03K19/01855 , H01L27/105 , Y10S257/904
摘要： A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.
摘要翻译：提供了一种半导体存储器件，其具有多个存储单元，每个存储单元包括一对具有N-导电型通道的交叉耦合的金属绝缘栅场效应晶体管，以及分别耦合到所述一对的多晶硅的一对负载电阻器交叉耦合晶体管。还提供外围电路，其由具有N导电型通道的金属绝缘栅场效应晶体管和具有P导电型通道的金属绝缘栅场效应晶体管构成。半导体存储器件形成在N型半导体衬底中，并且存储单元的一对交叉耦合金属绝缘栅场效应晶体管形成在与半导体形成PN结的P型阱区中底物有助于降低软错误的易感性。

5. 发明授权

US4300213A Memory circuit with increased operating speed 失效
标题翻译：内存电路具有提高的运行速度
公开(公告)号：US4300213A
公开(公告)日：1981-11-10
申请号：US89745
申请日：1979-10-31
申请人： Nobuyoshi Tanimura , Hiroshi Fukuta , Kotaro Nishimura , Tokumasa Yasui
发明人： Nobuyoshi Tanimura , Hiroshi Fukuta , Kotaro Nishimura , Tokumasa Yasui
IPC分类号： G11C11/412 , G11C11/417 , H03K19/0185 , H03K19/0944 , G11C7/00
CPC分类号： G11C11/412 , G11C11/417 , H03K19/018507 , H03K19/09443
摘要： Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.
摘要翻译：连接到由MISFET组成的存储单元的输入和输出端的数字线通过由解码器电路控制的开关电路耦合到公共数据线。还与数字线连接由多个以二极管形式串联连接的多个增强型MISFET组成的负载。数字线上的高电平信号通过负载装置的作用而降低。响应于数字线上的电位降低，开关装置在控制信号的早期上升时间被导通。结果，可以提高存储电路的工作速度。

6. 发明授权

US5359562A Semiconductor memory having polycrystalline silicon load resistors and CMOS peripheral circuitry 失效
标题翻译：具有多晶硅负载电阻器和CMOS外围电路的半导体存储器
公开(公告)号：US5359562A
公开(公告)日：1994-10-25
申请号：US684867
申请日：1991-04-15
申请人： Tokumasa Yasui , Shinji Shimizu , Kotaro Nishimura
发明人： Tokumasa Yasui , Shinji Shimizu , Kotaro Nishimura
IPC分类号： G11C11/412 , G11C11/418 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/11 , H03K19/0185 , G11C11/417 , G11C7/02
CPC分类号： G11C11/412 , G11C11/418 , H01L27/0688 , H01L27/0927 , H01L27/1112 , H03K19/01855 , H01L27/105 , Y10S257/904
摘要： A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.
摘要翻译：提供了一种半导体存储器件，其具有多个存储单元，每个存储单元包括一对具有N-导电型通道的交叉耦合的金属绝缘栅场效应晶体管，以及分别耦合到所述一对的多晶硅的一对负载电阻器交叉耦合晶体管。还提供外围电路，其由具有N导电型通道的金属绝缘栅场效应晶体管和具有P导电型通道的金属绝缘栅场效应晶体管构成。半导体存储器件形成在N型半导体衬底中，并且存储单元的一对交叉耦合金属绝缘栅场效应晶体管形成在与半导体形成PN结的P型阱区中底物有助于降低软错误的易感性。

7. 发明授权

US3949382A Misfet circuit for reading the state of charge 失效
标题翻译：用于读取充电状态的Misfet电路
公开(公告)号：US3949382A
公开(公告)日：1976-04-06
申请号：US515412
申请日：1974-10-16
申请人： Tokumasa Yasui
发明人： Tokumasa Yasui
IPC分类号： G11C11/405 , G11C11/4091 , G11C11/4094 , G11C7/06 , G11C11/24 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/4091
摘要： In an MIS type semiconductor memory device which has at least two parasitic capacitors and which delivers, at its outputs, the state of charge accumulated in at least one of the parasitic capacitors, the respective parasitic capacitors are provided with inverter circuits. Each of the inverter circuits receives, as an input signal, the state of charge accumulated in the corresponding parasitic capacitor. When charges accumulated by precharging are to be discharged, each inverter forms a discharging path for the opposite parasitic capacitor.
摘要翻译：在具有至少两个寄生电容器的MIS型半导体存储器件中，在其输出端传送累积在至少一个寄生电容器中的电荷状态，各个寄生电容器设置有反相器电路。每个逆变器电路作为输入信号接收累积在相应的寄生电容器中的电荷状态。当通过预充电积累的电荷被放电时，每个反相器形成相对的寄生电容器的放电路径。

8. 发明授权

US4554729A Method of making semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US4554729A
公开(公告)日：1985-11-26
申请号：US341623
申请日：1982-01-22
申请人： Nobuyoshi Tanimura , Tokumasa Yasui
发明人： Nobuyoshi Tanimura , Tokumasa Yasui
IPC分类号： G11C11/417 , G11C11/412 , H01L21/02 , H01L21/3215 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L21/28 , H01L21/26
CPC分类号： H01L28/20 , H01L21/32155 , H01L27/0288 , H01L27/0688 , H01L27/1112 , Y10S148/082
摘要： Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.
摘要翻译：这里公开了一种半导体存储器件，其由配备有具有保护电阻器和存储单元单元的栅极保护电路的外围电路单元组成，使得其可以用作MISFET型静态RAM，其特征在于，所述保护电阻器由具有与形成为合并到存储单元单元的负载电阻器中的上覆多晶硅膜的电阻率基本相同的电阻率的多晶硅膜制成。

9. 发明授权

US4712192A Semiconductor memory device and fabrication process thereof 失效
标题翻译：半导体存储器件及其制造工艺
公开(公告)号：US4712192A
公开(公告)日：1987-12-08
申请号：US783959
申请日：1985-10-04
申请人： Nobuyoshi Tanimura , Tokumasa Yasui
发明人： Nobuyoshi Tanimura , Tokumasa Yasui
IPC分类号： G11C11/417 , G11C11/412 , H01L21/02 , H01L21/3215 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , G11C13/00
CPC分类号： H01L28/20 , H01L21/32155 , H01L27/0288 , H01L27/0688 , H01L27/1112 , Y10S148/082
摘要： Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.
摘要翻译：这里公开了一种半导体存储器件，其由配备有具有保护电阻器和存储单元单元的栅极保护电路的外围电路单元组成，使得其可以用作MISFET型静态RAM，其特征在于，所述保护电阻器由具有与形成为合并到存储单元单元的负载电阻器中的上覆多晶硅膜的电阻率基本相同的电阻率的多晶硅膜制成。

10. 发明授权

US4564925A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4564925A
公开(公告)日：1986-01-14
申请号：US535056
申请日：1983-09-23
申请人： Yoshiaki Onishi, deceased , by Junko Onishi, administratrix , Hiroshi Kawamoto , Tokumasa Yasui
发明人： Yoshiaki Onishi, deceased , by Junko Onishi, administratrix , Hiroshi Kawamoto , Tokumasa Yasui
IPC分类号： G11C11/403 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096
摘要： A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals. In order to obtain a desirable pseudo-static memory, a data line precharge level is equalized to half of the supply voltage level, and the sense amplifier is constructed of a CMOS-FET latch circuit. As a result, the period of time from the change of the address signals until the delivery of the output data can be sufficiently shortened. It is therefore possible to form a pseudo-static memory which is, in effect, regarded as a static memory.
摘要翻译：半导体存储器具有诸如单MOS晶体管单元，检测所施加的地址信号的变化的检测器电路的动态存储单元以及接收检测器电路的检测输出的定时发生器电路。当地址信号改变时，从定时发生器电路响应地产生各种定时信号。响应于连续生成的定时信号，首先对存储器单元耦合的数据线进行预充电，并且在数据线的预充电之后选择一个存储单元。当读出放大器的操作开始时，从选择的存储单元传送到数据线的数据被放大。放大的数据通过类似地连续操作的列开关，主放大器，输出放大器等提供给外部端子。由于这种布置的半导体存储器形成伪静态存储器，所以它仅需要少量的外部定时信号。为了获得期望的伪静态存储器，将数据线预充电电平等于电源电压电平的一半，并且读出放大器由CMOS-FET锁存电路构成。结果，能够充分地缩短从地址信号变更直到输出数据传送的时间。因此，可以形成实际上被视为静态存储器的伪静态存储器。

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