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1. 发明授权

US06587388B2 Method and apparatus for reducing write operation time in dynamic random access memories 失效
公开(公告)号：US06587388B2
公开(公告)日：2003-07-01
申请号：US09844837
申请日：2001-04-27
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

2. 发明授权

US06829682B2 Destructive read architecture for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的破坏性读取架构
公开(公告)号：US06829682B2
公开(公告)日：2004-12-07
申请号：US09843504
申请日：2001-04-26
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G11C7/1006 , G11C2207/2245
摘要： A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
摘要翻译：公开了一种用于控制动态随机存取存储器（DRAM）系统的操作的方法，该DRAM系统具有被组织成行和列的多个存储单元。在本发明的示例性实施例中，该方法包括启用破坏性读取模式，该破坏性读取模式用于破坏性地读取存储在寻址的DRAM存储器单元中的位的位。信息的破坏性读取位被临时存储到临时存储设备中。延迟回写模式被使能，延迟回写模式用于将信息位在稍后的时间恢复到寻址的DRAM存储器单元。然后根据临时存储设备内的空间的可用性来调度延迟写回模式的执行。

3. 发明授权

US06404689B1 Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline 失效
标题翻译：在具有互锁管道的DRAM中隐藏刷新操作的方法和结构
公开(公告)号：US06404689B1
公开(公告)日：2002-06-11
申请号：US09822430
申请日：2001-03-30
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
IPC分类号： G11C700
CPC分类号： G11C7/1039 , G11C7/1072 , G11C11/406
摘要： Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRCext to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRCint after a plurality of external random access cycles n(tRCext) when enabling the corresponding internal random access operation n(tRCint). The additional core random access cycle time tRCint is achieved at every nth clock, where n>tRCint/(tRCext−tRCint), or at a time defined by the product of tRCext and tRCint/(tRCext−tRCint). The additional core cycle time tRCint is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.
摘要翻译：在DRAM或eDRAM中隐藏刷新操作是通过调整外部随机访问时间tRCext来略微延伸到内部随机访问周期中实现的。这允许在启用相应的内部随机访问操作n（tRCint）之后的多个外部随机访问周期n（tRCext）之后的额外的内部随机访问周期时间tRCint。在第n个时钟，其中n> tRCint /（tRCext-tRCint），或由tRCext和tRCint /（tRCext-tRCint）的乘积定义的时间，实现了额外的核随机访问周期时间tRCint。附加核心周期时间tRCint用于刷新DRAM通过调度等于或大于相位恢复时间的刷新刷新周期，可以使用DRAM单元实现完全命令兼容的静态随机存取时间。

4. 发明授权

US07404113B2 Flexible row redundancy system 有权
标题翻译：灵活的行冗余系统
公开(公告)号：US07404113B2
公开(公告)日：2008-07-22
申请号：US11031138
申请日：2005-01-07
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

5. 发明授权

US07146471B2 System and method for variable array architecture for memories 有权
标题翻译：用于存储器的可变阵列架构的系统和方法
公开(公告)号：US07146471B2
公开(公告)日：2006-12-05
申请号：US10748333
申请日：2003-12-31
申请人： Toshiaki Kirihata , Gerhard Mueller , Wing K. Luk
发明人： Toshiaki Kirihata , Gerhard Mueller , Wing K. Luk
IPC分类号： G06F12/02
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.
摘要翻译：公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

6. 发明授权

US07085180B2 Method and structure for enabling a redundancy allocation during a multi-bank operation 失效
标题翻译：在多行操作期间实现冗余分配的方法和结构
公开(公告)号：US07085180B2
公开(公告)日：2006-08-01
申请号：US10777596
申请日：2004-02-12
申请人： Gregory J. Fredeman , Mark D. Jacunski , Toshiaki Kirihata , Matthew R. Wordeman
发明人： Gregory J. Fredeman , Mark D. Jacunski , Toshiaki Kirihata , Matthew R. Wordeman
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/808 , G11C2029/0401 , G11C2029/2602
摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
摘要翻译：描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。该方法包括启用通过/故障位检测来激活给定的存储体的步骤。通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

7. 发明申请

US20050226083A1 DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCTIVE-READ MEMORY CACHE 失效
标题翻译：破坏性阅读随机访问记忆体系统与破坏性阅读记忆体缓存
公开(公告)号：US20050226083A1
公开(公告)日：2005-10-13
申请号：US11160220
申请日：2005-06-14
申请人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
发明人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
IPC分类号： G06F12/00 , G06F12/08 , G11C7/10 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/4093
CPC分类号： G11C8/12 , G06F12/0804 , G06F12/0893 , G06F12/0897 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093 , G11C2207/2245
摘要： A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.
摘要翻译：存储器存储系统包括多个存储器存储体和与之通信的高速缓冲存储器。多个存储器存储体和高速缓存还包括配置用于对其进行延迟回写调度的破坏性读取存储器存储元件。

8. 发明授权

US06845059B1 High performance gain cell architecture 失效
标题翻译：高性能增益单元架构
公开(公告)号：US06845059B1
公开(公告)日：2005-01-18
申请号：US10604109
申请日：2003-06-26
申请人： Matthew R. Wordeman , John E. Barth , Toshiaki Kirihata
发明人： Matthew R. Wordeman , John E. Barth , Toshiaki Kirihata
IPC分类号： G11C7/10 , G11C8/16 , G11C11/406 , G11C11/4096 , G11C8/00
CPC分类号： G11C8/16 , G11C7/106 , G11C7/1087 , G11C11/40603 , G11C11/40615
摘要： A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.
摘要翻译：描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元格，同时读出数组中另一个字线上的单元格。通过实现读出放大器的阵列，使得一个放大器耦合到每个读取位线，以及一个接收感测数据的结果并将该数据传送到写入数据线的锁存器，可以“管理”读出和读周期的回写阶段。这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段的写周期，允许它们同时发生。该架构优选采用非破坏性读取存储器单元，例如2T或3T增益单元，通过较小和更多的SER免疫存储单元实现SRAM类周期和访问时间。

9. 发明授权

US06674673B1 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权
公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
申请人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
发明人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

10. 发明授权

US06400639B1 Wordline decoder system and method 失效
标题翻译：字线解码器系统和方法
公开(公告)号：US06400639B1
公开(公告)日：2002-06-04
申请号：US09712628
申请日：2000-11-14
申请人： Brian L. Ji , Toshiaki Kirihata , Dmitry G. Netis
发明人： Brian L. Ji , Toshiaki Kirihata , Dmitry G. Netis
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/08
摘要： A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.
摘要翻译：公开了一种存储器解码器系统。在本发明的示例性实施例中，系统包括排列成行和列的存储器单元阵列，其中多个字线驱动器对应于矩阵中的每一行。一组字线驱动器 - 解码器块每个包含多个字线驱动器的子集，其中每个字线驱动器 - 解码器块由行控制块分隔。行控制块包括用于字线驱动器的控制电路。对于任何给定的字线驱动器 - 解码器块，其中包含的第一组字线驱动器由位于给定字线驱动器 - 解码器块的一侧上的行控制块控制，而其中包含的第二组字线驱动器由行控制块位于给定字线驱动器 - 解码器块的相对侧。

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