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1. 发明授权

US06404689B1 Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline 失效
标题翻译：在具有互锁管道的DRAM中隐藏刷新操作的方法和结构
公开(公告)号：US06404689B1
公开(公告)日：2002-06-11
申请号：US09822430
申请日：2001-03-30
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
IPC分类号： G11C700
CPC分类号： G11C7/1039 , G11C7/1072 , G11C11/406
摘要： Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRCext to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRCint after a plurality of external random access cycles n(tRCext) when enabling the corresponding internal random access operation n(tRCint). The additional core random access cycle time tRCint is achieved at every nth clock, where n>tRCint/(tRCext−tRCint), or at a time defined by the product of tRCext and tRCint/(tRCext−tRCint). The additional core cycle time tRCint is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.
摘要翻译：在DRAM或eDRAM中隐藏刷新操作是通过调整外部随机访问时间tRCext来略微延伸到内部随机访问周期中实现的。这允许在启用相应的内部随机访问操作n（tRCint）之后的多个外部随机访问周期n（tRCext）之后的额外的内部随机访问周期时间tRCint。在第n个时钟，其中n> tRCint /（tRCext-tRCint），或由tRCext和tRCint /（tRCext-tRCint）的乘积定义的时间，实现了额外的核随机访问周期时间tRCint。附加核心周期时间tRCint用于刷新DRAM通过调度等于或大于相位恢复时间的刷新刷新周期，可以使用DRAM单元实现完全命令兼容的静态随机存取时间。

2. 发明授权

US06674676B1 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权
标题翻译：用于微电池嵌入式DRAM（e-DRAM）架构的列冗余系统和方法
公开(公告)号：US06674676B1
公开(公告)日：2004-01-06
申请号：US10444226
申请日：2003-05-23
申请人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
发明人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
摘要翻译：一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与访问用于写操作的第二微小区。如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。

3. 发明申请

US20050226083A1 DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCTIVE-READ MEMORY CACHE 失效
标题翻译：破坏性阅读随机访问记忆体系统与破坏性阅读记忆体缓存
公开(公告)号：US20050226083A1
公开(公告)日：2005-10-13
申请号：US11160220
申请日：2005-06-14
申请人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
发明人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
IPC分类号： G06F12/00 , G06F12/08 , G11C7/10 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/4093
CPC分类号： G11C8/12 , G06F12/0804 , G06F12/0893 , G06F12/0897 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093 , G11C2207/2245
摘要： A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.
摘要翻译：存储器存储系统包括多个存储器存储体和与之通信的高速缓冲存储器。多个存储器存储体和高速缓存还包括配置用于对其进行延迟回写调度的破坏性读取存储器存储元件。

4. 发明授权

US06674673B1 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权
公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
申请人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
发明人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

5. 发明授权

US06948028B2 Destructive-read random access memory system buffered with destructive-read memory cache 失效
标题翻译：破坏性读取随机存取存储器系统用破坏性内存缓存缓冲
公开(公告)号：US06948028B2
公开(公告)日：2005-09-20
申请号：US10710169
申请日：2004-06-23
申请人： Brian L. Ji , Chorng-Lii Hwang , Toshiaki K. Kirihata , Seiji Munetoh
发明人： Brian L. Ji , Chorng-Lii Hwang , Toshiaki K. Kirihata , Seiji Munetoh
IPC分类号： G06F12/00 , G06F12/08 , G11C7/10 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/4093
CPC分类号： G11C8/12 , G06F12/0804 , G06F12/0893 , G06F12/0897 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093 , G11C2207/2245
摘要： A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.
摘要翻译：公开了一种存储器存储系统。在示例性实施例中，存储器存储系统包括多个存储器存储体和与其通信的高速缓存器。多个存储器存储体和高速缓存还包括破坏性读取存储器存储元件。

6. 发明授权

US06445611B1 Method and arrangement for preconditioning in a destructive read memory 失效
标题翻译：在破坏性读取存储器中预处理的方法和装置
公开(公告)号：US06445611B1
公开(公告)日：2002-09-03
申请号：US09966142
申请日：2001-09-28
申请人： John A. Fifield , Chorng-Lii Hwang , Daniel W. Storaska
发明人： John A. Fifield , Chorng-Lii Hwang , Daniel W. Storaska
IPC分类号： G11C1124
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/408 , G11C2207/104
摘要： An arrangement and method is disclosed which works toward shortening the machine cycle of a DRAM. A data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a low state or a high state is written to the storage capacitor. In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. This cycle may include the reading of a stored data value from the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level, as by clamping the bitline through a bitline restore device. The wordline is then deactivated. Subsequently, the wordline is activated again during a write cycle to write one of a low state and a high state to the storage capacitor to indicate a stored data value.
摘要翻译：公开了用于缩短DRAM的机器周期的布置和方法。将数据值写入到DRAM的存储单元的存储电容器中，将数据值存储在存储电容器中作为低状态和高状态之一。在第一字线激活周期期间，存储电容器被预处理成预处理的电压电平。在随后的字线激活周期中，将低状态或高状态写入存储电容器。在本发明的一个方面，字线在第一字线激活周期中被激活，以开始清除存储电容器的任何先前存储的状态。该周期可以包括从存储电容器读取存储的数据值。然后，紧接其后，在保持字线被激活的同时，将存储电容器预先处理为预处理的电压电平，如通过位线恢复装置夹紧位线。然后禁用字线。随后，在写入周期期间再次激活字线以将低状态和高状态中的一个写入存储电容器以指示存储的数据值。

7. 发明授权

US5898706A Structure and method for reliability stressing of dielectrics 失效
标题翻译：电介质可靠性应力的结构和方法
公开(公告)号：US5898706A
公开(公告)日：1999-04-27
申请号：US846989
申请日：1997-04-30
申请人： Roger Aime Dufresne , Charles William Griffin , Chorng-Lii Hwang , William Alan Klaasen , Alvin Wayne Strong
发明人： Roger Aime Dufresne , Charles William Griffin , Chorng-Lii Hwang , William Alan Klaasen , Alvin Wayne Strong
IPC分类号： G01R31/28 , G01R31/12
CPC分类号： G01R31/2877 , G01R31/2856
摘要： The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.
摘要翻译：本发明涉及一种用于集成电路的可靠性测试的装置和方法。本发明提供了一种用于测试集成电路的栅极和节点电介质的测试结构和方法，其中自加热栅结构与产品结构本身集成。产品结构内的所选导线用作加热元件，以提供集成电路的温度应力。局部自加热门结构是产品芯片的组成部分。因此，测试结构的蚀刻和沉积特性保持与产品本身的蚀刻和沉积特性相同。由于低压技术使得由于电压应力而难以获得显着的加速度，所以可以使用温度应力来增加加速度。

8. 发明授权

US5587614A Microplanarization of rough electrodes by thin amorphous layers 失效
标题翻译：粗电极由薄的非晶层微观平面化
公开(公告)号：US5587614A
公开(公告)日：1996-12-24
申请号：US473807
申请日：1995-06-07
申请人： Chorng-Lii Hwang , Clarence W. Teng
发明人： Chorng-Lii Hwang , Clarence W. Teng
IPC分类号： H01L21/02 , H01L21/768 , H01L27/02 , H01L27/00
CPC分类号： H01L28/40 , H01L21/7684
摘要： A method of improving the dielectric properties of a thin dielectric disposed on a polycrystalline material, a method of forming a capacitor therewith and the capacitor. An electrode (17) having a polycrystalline material surface having voids (23) extending to the surface, preferably silicon, is provided. A layer of an amorphous form of the material (19) having a thickness of from about 20 .ANG. to about 500 .ANG. is formed over the surface with the amorphous layer disposed within the voids. A thin layer of a dielectric (21) is formed over the amorphous layer and, in the fabrication of a capacitor, a layer of electrical conductor (25) is provided which is spaced from the material over the dielectric. A microcontaminant can be disposed between the polycrystalline material surface and the amorphous layer.
摘要翻译：一种改善设置在多晶材料上的薄电介质的介电性能的方法，与其形成电容器的方法和电容器。提供具有多晶材料表面的电极（17），其具有延伸到表面的空隙（23），优选为硅。在表面上形成厚度为约20埃至约500埃的材料（19）的无定形形式的层，其中非晶层设置在空隙内。电介质（21）的薄层形成在非晶层之上，并且在电容器的制造中，提供与电介质上的材料间隔开的电导体层（25）。微量微粒可以设置在多晶材料表面和非晶层之间。

9. 发明授权

US06621294B2 Pad system for an integrated circuit or device 失效
标题翻译：用于集成电路或器件的Pad系统
公开(公告)号：US06621294B2
公开(公告)日：2003-09-16
申请号：US10037660
申请日：2002-01-03
申请人： Louis L. Hsu , Li-Kong Wang , Chorng-Lii Hwang
发明人： Louis L. Hsu , Li-Kong Wang , Chorng-Lii Hwang
IPC分类号： H03K1920
CPC分类号： H03K19/1737
摘要： The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.
摘要翻译：本发明提供了一种用于集成电路或装置的焊盘系统。垫系统包括具有至少一个焊盘输入端子的逻辑电路，用于连接至少一个焊盘和至少两个用于连接到集成电路或设备的至少一个电路系统的输出端子。逻辑电路可配置为在集成电路或器件的至少一个电路系统的至少两个点之间选择性地连接至少一个焊盘。

10. 发明授权

US06440638B2 Method and apparatus for resist planarization 失效
标题翻译：抗蚀剂平面化方法和装置
公开(公告)号：US06440638B2
公开(公告)日：2002-08-27
申请号：US09161854
申请日：1998-09-28
申请人： John Golz , Chorng-Lii Hwang , John Zhu
发明人： John Golz , Chorng-Lii Hwang , John Zhu
IPC分类号： G03C500
CPC分类号： H01L21/31058 , G03F7/168 , G03F7/2026
摘要： A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.
摘要翻译：用于平坦化基板上的光致抗蚀剂层的方法。光致抗蚀剂层暴露于光致抗蚀剂敏感的辐射波长。相对于光致抗蚀剂层的主要尺寸，辐射以相对于光致抗蚀剂层的主要尺寸的倾斜角指向光致抗蚀剂层。显影光致抗蚀剂。

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