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1. 发明授权

US06829682B2 Destructive read architecture for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的破坏性读取架构
公开(公告)号：US06829682B2
公开(公告)日：2004-12-07
申请号：US09843504
申请日：2001-04-26
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G11C7/1006 , G11C2207/2245
摘要： A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
摘要翻译：公开了一种用于控制动态随机存取存储器（DRAM）系统的操作的方法，该DRAM系统具有被组织成行和列的多个存储单元。在本发明的示例性实施例中，该方法包括启用破坏性读取模式，该破坏性读取模式用于破坏性地读取存储在寻址的DRAM存储器单元中的位的位。信息的破坏性读取位被临时存储到临时存储设备中。延迟回写模式被使能，延迟回写模式用于将信息位在稍后的时间恢复到寻址的DRAM存储器单元。然后根据临时存储设备内的空间的可用性来调度延迟写回模式的执行。

2. 发明授权

US06990025B2 Multi-port memory architecture 有权
标题翻译：多端口内存架构
公开(公告)号：US06990025B2
公开(公告)日：2006-01-24
申请号：US10604994
申请日：2003-08-29
申请人： Toshiaki Kirihata , Hoki Kim , Matthew Wordeman
发明人： Toshiaki Kirihata , Hoki Kim , Matthew Wordeman
IPC分类号： G11C7/00
CPC分类号： G11C11/405 , G11C8/16 , G11C11/4099
摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.
摘要翻译：描述了利用读取位线的开放位线配置的多端口存储器架构。存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。每个存储器阵列包括耦合到参考单元的参考字线。当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

3. 发明申请

US20050047218A1 MULTI-PORT MEMORY ARCHITECTURE 有权
标题翻译：多端口存储器架构
公开(公告)号：US20050047218A1
公开(公告)日：2005-03-03
申请号：US10604994
申请日：2003-08-29
申请人： Toshiaki Kirihata , Hoki Kim , Matthew Wordeman
发明人： Toshiaki Kirihata , Hoki Kim , Matthew Wordeman
IPC分类号： G11C5/00 , G11C8/16 , G11C11/405 , G11C11/4099
CPC分类号： G11C11/405 , G11C8/16 , G11C11/4099
摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.
摘要翻译：描述了利用读取位线的开放位线配置的多端口存储器架构。存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。每个存储器阵列包括耦合到参考单元的参考字线。当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

4. 发明申请

US20050193253A1 A Command Multiplier for Built-In-Self-Test 有权
标题翻译：用于内置自检的命令乘数
公开(公告)号：US20050193253A1
公开(公告)日：2005-09-01
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
发明人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
IPC分类号： G06F11/00 , G11C29/14 , G11C29/16
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译：公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

5. 发明申请

US20050180230A1 Method and structure for enabling a redundancy allocation during a multi-bank operation 失效
标题翻译：在多行操作期间实现冗余分配的方法和结构
公开(公告)号：US20050180230A1
公开(公告)日：2005-08-18
申请号：US10777596
申请日：2004-02-12
申请人： Gregory Fredeman , Mark Jacunski , Toshiaki Kirihata , Matthew Wordeman
发明人： Gregory Fredeman , Mark Jacunski , Toshiaki Kirihata , Matthew Wordeman
IPC分类号： G11C7/00 , G11C29/00 , G11C29/40 , G11C29/44
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/808 , G11C2029/0401 , G11C2029/2602
摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
摘要翻译：描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。该方法包括启用通过/故障位检测来激活给定的存储体的步骤。通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

6. 发明申请

US20070223298A1 Differential and Hierarchical Sensing for Memory Circuits 有权
标题翻译：用于存储器电路的差分和分层检测
公开(公告)号：US20070223298A1
公开(公告)日：2007-09-27
申请号：US11754422
申请日：2007-05-29
申请人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
发明人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译：存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

7. 发明申请

US20070235708A1 Programmable via structure for three dimensional integration technology 有权
标题翻译：可编程通孔结构，用于三维集成技术
公开(公告)号：US20070235708A1
公开(公告)日：2007-10-11
申请号：US11393270
申请日：2006-03-30
申请人： Bruce Elmegreen , Lia Krusin-Elbaum , Chung Lam , Dennis Newns , Matthew Wordeman , Albert Young
发明人： Bruce Elmegreen , Lia Krusin-Elbaum , Chung Lam , Dennis Newns , Matthew Wordeman , Albert Young
IPC分类号： H01L29/04
CPC分类号： H01L45/144 , H01L23/5226 , H01L23/5252 , H01L23/5256 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L2924/0002 , H01L2924/00
摘要： A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
摘要翻译：用于三维积分（3DI）半导体器件的可编程链路结构包括至少部分地填充有相变材料（PCM）和靠近PCM的加热装置的通孔。加热装置被配置为将PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态。因此，通路限定位于其一端的输入连接与位于其另一端的输出连接之间的可编程连接。

8. 发明申请

US20070025170A1 Differential and hierarchical sensing for memory circuits 失效
公开(公告)号：US20070025170A1
公开(公告)日：2007-02-01
申请号：US11190542
申请日：2005-07-27
申请人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
发明人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

9. 发明申请

US20070235784A1 Three-terminal cascade switch for controlling static power consumption in integrated circuits 失效
标题翻译：用于控制集成电路静态功耗的三端子级联开关
公开(公告)号：US20070235784A1
公开(公告)日：2007-10-11
申请号：US11393259
申请日：2006-03-30
申请人： Lia Krusin-Elbaum , Dennis Newns , Matthew Wordeman
发明人： Lia Krusin-Elbaum , Dennis Newns , Matthew Wordeman
IPC分类号： H01L29/94
CPC分类号： H01L45/1226 , H01L27/24 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/148
摘要： A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.
摘要翻译：配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料（PCM）开关器件。每个PCM开关装置还包括设置在第一端子和第二端子之间接触的PCM，在第二端子和第三端子之间接触地设置的加热装置，加热装置位于PCM附近，并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

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