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1. 发明授权

US5426745A Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition 失效
标题翻译：装置包括具有不同功能的一对神经网络，协同执行指令识别
公开(公告)号：US5426745A
公开(公告)日：1995-06-20
申请号：US206195
申请日：1994-03-03
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。分别设置在语音，图像和指令识别单元中的至少两个中的神经网络，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音进行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

2. 发明授权

US5163111A Customized personal terminal device 失效
标题翻译：定制个人终端设备
公开(公告)号：US5163111A
公开(公告)日：1992-11-10
申请号：US567010
申请日：1990-08-14
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。神经网络提供在语音，图像和指令识别单元中的至少两个中，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音执行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

3. 发明申请

US20060034452A1 Code calculating device 审中-公开
标题翻译：代码计算设备
公开(公告)号：US20060034452A1
公开(公告)日：2006-02-16
申请号：US10518481
申请日：2002-06-20
申请人： Motonobu Tonomura , Yuki Kondoh
发明人： Motonobu Tonomura , Yuki Kondoh
IPC分类号： H04L9/00
CPC分类号： H04L9/304 , G06F7/724 , G06F7/725 , H03M13/15 , H04L1/0061 , H04L9/3066 , H04L2209/12
摘要： A code computing apparatus with an error detection code (CRC) generating function and an elliptic curve cryptography (ECC) function, comprising a matrix element computation part 30 for generating matrix elements from parameter values set in first and second registers 201 and 202, a matrix element register 51 for holding the matrix elements generated by the matrix element computation part, and an inner product calculation part 40 for executing inner product calculation between the matrix elements held by the matrix element register and data set in a third register. The matrix element computation part selectively generates matrix elements for error detection and matrix elements for encryption by changing the parameters to be set in the first and second registers, and the inner product calculation part is shared to error control code generation and data encryption by altering the matrix elements to be held in the matrix element register.
摘要翻译：具有错误检测码（CRC）生成函数和椭圆曲线密码（ECC）函数的代码计算装置，包括用于从在第一和第二寄存器201和202中设置的参数值生成矩阵元素的矩阵元素计算部分30，矩阵用于保持由矩阵元素计算部分生成的矩阵元素的元素寄存器51，以及用于执行由矩阵元素寄存器保持的矩阵元素与第三寄存器中设置的数据之间的内积计算的内积计算部40。矩阵元素计算部通过改变要设置在第一和第二寄存器中的参数来选择性地生成用于错误检测的矩阵元素和用于加密的矩阵元素，并且通过改变内部乘积计算部分来进行错误控制代码生成和数据加密要保存在矩阵元素寄存器中的矩阵元素。

4. 发明授权

US5119499A Host processor which includes apparatus for performing coprocessor functions 失效
标题翻译：主处理器，其包括用于执行协处理器功能的装置
公开(公告)号：US5119499A
公开(公告)日：1992-06-02
申请号：US356422
申请日：1989-05-25
申请人： Motonobu Tonomura , Seigzumi Matsui , Kouji Hashimoto
发明人： Motonobu Tonomura , Seigzumi Matsui , Kouji Hashimoto
IPC分类号： G06F9/38 , G06F15/80
CPC分类号： G06F15/8015 , G06F9/3877 , G06F9/3879
摘要： The execution of an instruction for one of co-processors is subrogated by information processing function implemented in the host-processor. When a co-processor identification code involved in the instruction for the co-processor agrees with a host-processor internal processing identification code set in the host-processor, the instruction decoder of the host-processor starts the information subrogating processing function. Thus, protocol control for communication from the host-processor to co-processors can be omitted so that a high-speed data processing becomes possible.
摘要翻译：通过在主机处理器中实现的信息处理功能代替协处理器之一的指令的执行。当涉及协处理器的指令的协处理器识别码与主机处理器中设置的主机处理器内部处理识别码一致时，主机处理器的指令解码器启动信息代位处理功能。因此，可以省略从主机处理器到协处理器的通信的协议控制，使得可以进行高速数据处理。

5. 发明授权

US08363981B2 Image converter and image converting method 有权
标题翻译：图像转换器和图像转换方法
公开(公告)号：US08363981B2
公开(公告)日：2013-01-29
申请号：US12331514
申请日：2008-12-10
申请人： Motonobu Tonomura
发明人： Motonobu Tonomura
IPC分类号： G06K9/32 , G09G5/00 , H04N9/74 , G06F7/38
CPC分类号： G06T3/0031
摘要： On conversion of a distorted circular image photographed by use of a fisheye lens to a planar regular image, parameter setting is performed by a user's intuitive manipulation to relieve the operation load. A dome-shaped virtual sphere H is defined on a distorted circular image S on the XY plane, and a user is allowed to designate a cut-out center point P (x0, y0) and an auxiliary point Q (x1, y1) on the distorted circular image S. An intersecting point G (x0, y0, z0) immediately above the point P is determined, and a UV plane is defined on a tangent plane S2 with respect to the virtual sphere H. An angle φ formed between the U axis and the X axis is determined on the basis of an angle θ formed between a reference straight line J passing through two points P, Q and the X axis. Transformation equations based on the orthogonal projection method including the coordinate values x0, y0, z0 and the angle φ as parameters are utilized to allow the coordinates (u, v) to correspond to coordinates (x, y), a distance between the two points P, Q is given as a conversion magnification m, thereby a part in the vicinity of the point P of the distorted circular image S is converted to a plane regular image on the UV plane.
摘要翻译：在通过使用鱼眼镜头拍摄的失真圆形图像转换为平面正常图像时，通过用户的直观操作来执行参数设置以减轻操作负载。圆弧形虚拟球体H被定义在XY平面上的失真圆形图像S上，并且允许用户将切出的中心点P（x0，y0）和辅助点Q（x1，y1）指定在确定畸变的圆形图像S.确定在点P正上方的交点G（x0，y0，z0），并且在相对于虚拟球体H的切平面S2上定义UV平面。基于角度θ来确定在U轴和X轴之间形成的轴线; 形成在通过两点P，Q和X轴的基准直线J之间。基于正交投影方法的变换方程，包括坐标值x0，y0，z0和角度＆phgr; 作为参数用于允许坐标（u，v）对应于坐标（x，y），两个点P，Q之间的距离被给定为转换倍率m，因此点P附近的一部分的失真圆形图像S在UV平面上转换为平面正常图像。

6. 发明授权

US06772186B1 Multimedia multiply-adder 有权
标题翻译：多媒体加法器
公开(公告)号：US06772186B1
公开(公告)日：2004-08-03
申请号：US09618560
申请日：2000-07-18
申请人： Motonobu Tonomura , Fumio Arakawa
发明人： Motonobu Tonomura , Fumio Arakawa
IPC分类号： G06F752
CPC分类号： G06F7/5443 , G06F7/4991 , G06F7/49994 , G06F7/5318 , G06F2207/3828
摘要： A multimedia processor is capable of concurrently carrying out processing tasks at different degrees of precision suitable for a variety of purposes and displays high performance of consecutively outputting a new cumulative result by adding or subtracting a result of multiplication to or from an existing cumulative result. To prevent the processing precision from deteriorating in applications where the processing precision is critical, critical processing precision is assured by multiplication of a signed number by an unsigned number. A partial product output by a multiplication and an existing cumulative result are supplied. The number of inputs is counted by a carry-save counter based on a 7-3 counter. A ripple adder is employed on the low-order-digit side where propagation of carry is completed early. On the other hand, a carry select/look-ahead adder is employed on the high-order-digit side to speed up the propagation of a carry. In this way, a multimedia multiply adder/subtractor can be assembled with a small number of gate stages. As a result, there is exhibited an effect that, when it is desired to store a series of multiplication results obtained consecutively, a carry-save result produced in a middle of one machine cycle can be input and stored for further use when an eventual result of propagation of a carry can not be output during the one machine cycle.
摘要翻译：多媒体处理器能够以适合各种目的的不同精度的同时执行处理任务，并且通过将现有累积结果的乘法结果相加或相减来连续地输出新的累积结果的高性能。为了防止处理精度在处理精度至关重要的应用中处理精度降低，通过将有符号数乘以无符号数来确保关键处理精度。提供乘法和现有累积结果的部分乘积输出。基于7-3计数器的进位保存计数器对输入数进行计数。在进位传播早期完成的低位数字侧采用纹波加法器。另一方面，在高位数侧采用进位选择/预读加法器，以加速进位的传播。以这种方式，多路复用加法器/减法器可以用少量门级组合。结果，显示了当希望存储连续获得的一系列相乘结果时，可以输入并存储在一个机器周期的中间产生的进位保存结果，以便在最终结果时进一步使用在一个机器周期期间不能输出进位的传播。

7. 发明授权

US06493255B2 Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件和采用半导体集成电路器件的信息处理器件
公开(公告)号：US06493255B2
公开(公告)日：2002-12-10
申请号：US10024008
申请日：2001-12-21
申请人： Osamu Nishii , Motonobu Tonomura , Takanobu Tsunoda
发明人： Osamu Nishii , Motonobu Tonomura , Takanobu Tsunoda
IPC分类号： G11C1100
CPC分类号： G11C15/04
摘要： A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is provided. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.
摘要翻译：提供了一个小面积的联想记忆，用于通过加法产生的值与减少的进位延迟相关联。相邻的1位存储器值和取决于相邻2位的相加输入的信号被输入到使用MOS晶体管构成的CAM存储单元中，并且根据输入值将命中线拉下或上拉。

8. 发明授权

US08265427B2 Interpolator and designing method thereof 有权
标题翻译：插值器及其设计方法
公开(公告)号：US08265427B2
公开(公告)日：2012-09-11
申请号：US12917766
申请日：2010-11-02
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06K9/36
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

9. 发明授权

US08000563B2 Interpolation device 有权
标题翻译：插值装置
公开(公告)号：US08000563B2
公开(公告)日：2011-08-16
申请号：US11891207
申请日：2007-08-09
申请人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
发明人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
IPC分类号： G06K9/00 , G06K9/40 , G06K9/32 , G06F7/38
CPC分类号： H04N9/045 , G06T3/4015 , G09G5/02 , G09G2340/0428 , G09G2340/06 , G09G2340/14 , G09G2360/16 , H04N2209/046
摘要： An interpolation process for scaling is performed directly on raw data from an image pickup apparatus. Raw data, constituted by inputted Bayer pattern array are as a set of pixels positioned on respective lattice points on a square lattice. A position of an interpolation point Q is designated by an upper address that indicates a lattice point near the upper left and a lower address that indicates a position inside a lattice frame, a specific color is designated for which a pixel value is to be determined. An interpolation reference frame is determined, formed of a smallest square, which contains the interpolation point Q and with which the four vertices are formed by lattice points of the designated color, and an interpolation origin, constituted by the upper left lattice point of the interpolation reference frame, interpolation proportions d* and e* are determined. An interpolation calculation is performed.
摘要翻译：直接对来自图像拾取装置的原始数据执行缩放的插值处理。由输入的拜耳图案阵列构成的原始数据是位于正方形格子上的相应格子点上的一组像素。内插点Q的位置由指示靠近左上角的格点的上部地址和表示格子框内的位置的下部地址指定，指定要确定像素值的特定颜色。确定由包含内插点Q并且由指定颜色的格点形成四个顶点的最小平方形的内插参考帧，以及由插值的左上方格点构成的插值原点参考帧，插值比例d *和e *被确定。执行插值计算。

10. 发明授权

US07840623B2 Interpolator and designing method thereof 有权
标题翻译：插值器及其设计方法
公开(公告)号：US07840623B2
公开(公告)日：2010-11-23
申请号：US11523351
申请日：2006-09-19
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06F7/38
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

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