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1. 发明授权

US08000563B2 Interpolation device 有权
标题翻译：插值装置
公开(公告)号：US08000563B2
公开(公告)日：2011-08-16
申请号：US11891207
申请日：2007-08-09
申请人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
发明人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
IPC分类号： G06K9/00 , G06K9/40 , G06K9/32 , G06F7/38
CPC分类号： H04N9/045 , G06T3/4015 , G09G5/02 , G09G2340/0428 , G09G2340/06 , G09G2340/14 , G09G2360/16 , H04N2209/046
摘要： An interpolation process for scaling is performed directly on raw data from an image pickup apparatus. Raw data, constituted by inputted Bayer pattern array are as a set of pixels positioned on respective lattice points on a square lattice. A position of an interpolation point Q is designated by an upper address that indicates a lattice point near the upper left and a lower address that indicates a position inside a lattice frame, a specific color is designated for which a pixel value is to be determined. An interpolation reference frame is determined, formed of a smallest square, which contains the interpolation point Q and with which the four vertices are formed by lattice points of the designated color, and an interpolation origin, constituted by the upper left lattice point of the interpolation reference frame, interpolation proportions d* and e* are determined. An interpolation calculation is performed.
摘要翻译：直接对来自图像拾取装置的原始数据执行缩放的插值处理。由输入的拜耳图案阵列构成的原始数据是位于正方形格子上的相应格子点上的一组像素。内插点Q的位置由指示靠近左上角的格点的上部地址和表示格子框内的位置的下部地址指定，指定要确定像素值的特定颜色。确定由包含内插点Q并且由指定颜色的格点形成四个顶点的最小平方形的内插参考帧，以及由插值的左上方格点构成的插值原点参考帧，插值比例d *和e *被确定。执行插值计算。

2. 发明申请

US20080056618A1 Interpolation device 有权
标题翻译：插值装置
公开(公告)号：US20080056618A1
公开(公告)日：2008-03-06
申请号：US11891207
申请日：2007-08-09
申请人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
发明人： Kyouji Yoshino , Motonobu Tonomura , Hajime Seino
IPC分类号： G06K9/32
CPC分类号： H04N9/045 , G06T3/4015 , G09G5/02 , G09G2340/0428 , G09G2340/06 , G09G2340/14 , G09G2360/16 , H04N2209/046
摘要： An interpolation process for scaling is performed directly on raw data from an image pickup apparatus. Raw data, constituted of Bayer pattern array pixels input by a pixel value input unit 110 are stored in a pixel value storage unit 120 as a set of pixels positioned on respective lattice points on a square lattice. An interpolation point designating unit 170 designates a position of an interpolation point Q by an upper address that indicates a lattice point near the upper left and a lower address that indicates a position inside a lattice frame, and a calculation target color designating unit 160 designates a specific color for which a pixel value is to be determined. An interpolation reference frame determining unit 150 determines an interpolation reference frame, formed of a smallest square, which contains the interpolation point Q and with which the four vertices are formed by lattice points of the designated color, and an interpolation origin, constituted of the upper left lattice point of the interpolation reference frame, and an interpolation proportion determining unit 140 determines interpolation proportions d* and e* based on distances between the interpolation origin and the interpolation point Q. An interpolation calculation unit 130 performs an interpolation calculation using pixel values of the surroundings of the interpolation reference frame and the interpolation proportions d* and e*.
摘要翻译：直接对来自图像拾取装置的原始数据执行缩放的插值处理。由像素值输入单元110输入的拜耳图案阵列像素构成的原始数据作为位于正方格子上的各个格点上的一组像素存储在像素值存储单元120中。内插点指定单元170将内插点Q的位置指定指示靠近左上角的格点的上部地址和指示格子框内的位置的下部地址，并且计算对象颜色指定单元160指定要确定像素值的特定颜色。内插基准帧确定单元150确定包含内插点Q并且由指定颜色的格点形成四个顶点的最小平方形的内插参考帧，以及由上部插值比例确定单元140基于插值原点和内插点Q之间的距离来确定内插比例d *和e *。插值计算单元130使用插值原点和内插点Q的像素值进行插值计算插值参考帧的周围和插值比例d *和e *。

3. 发明申请

US20110044562A1 INTERPOLATOR AND DESIGNING METHOD THEREOF 有权
公开(公告)号：US20110044562A1
公开(公告)日：2011-02-24
申请号：US12917766
申请日：2010-11-02
申请人： Motonobu TONOMURA , Kyouji Yoshino
发明人： Motonobu TONOMURA , Kyouji Yoshino
IPC分类号： G06K9/32
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.

4. 发明申请

US20110055304A1 INTERPOLATOR AND DESIGNING METHOD THEREOF 失效
标题翻译：插值器及其设计方法
公开(公告)号：US20110055304A1
公开(公告)日：2011-03-03
申请号：US12917655
申请日：2010-11-02
申请人： Motonobu TONOMURA , Kyouji Yoshino
发明人： Motonobu TONOMURA , Kyouji Yoshino
IPC分类号： G06F17/17
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）来计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

5. 发明申请

US20070136409A1 Interpolator and designing method thereof 有权
标题翻译：插值器及其设计方法
公开(公告)号：US20070136409A1
公开(公告)日：2007-06-14
申请号：US11523351
申请日：2006-09-19
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06F7/38
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于4位值A（位a 3，a 2，...，N 2，...，N 2）来计算内插值C， SUB）和B（表示负数）的B（位b 3 3 b 2 2 b 0）补码表示法和4位内插速率D（位d 3 3 d 2 2 d 1 d 0 0）组成只有小数部分，C =（1-D）* A + D * B的基本表达式被转换成由无符号部分组成的表达式，该表达式包括具有位d （i = 0,1,2和3）的逻辑反相值e i i i i i i，并且表示内插值C的绝对值以及指示内插值C的符号的有符号部分。然后，从无符号部分的算术运算生成位c 6至C 0 0的7位，并且通过考虑来自算术的位c 6的数字的进位来执行有符号部分的逻辑判断无符号部分的操作生成位c <7> 。获得的8位值（位c <7>至c 0）的有效数字作为内插值被输出。

6. 发明授权

US08265427B2 Interpolator and designing method thereof 有权
标题翻译：插值器及其设计方法
公开(公告)号：US08265427B2
公开(公告)日：2012-09-11
申请号：US12917766
申请日：2010-11-02
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06K9/36
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

7. 发明授权

US07840623B2 Interpolator and designing method thereof 有权
标题翻译：插值器及其设计方法
公开(公告)号：US07840623B2
公开(公告)日：2010-11-23
申请号：US11523351
申请日：2006-09-19
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06F7/38
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

8. 发明授权

US08671126B2 Interpolator and designing method thereof 失效
标题翻译：插值器及其设计方法
公开(公告)号：US08671126B2
公开(公告)日：2014-03-11
申请号：US12917655
申请日：2010-11-02
申请人： Motonobu Tonomura , Kyouji Yoshino
发明人： Motonobu Tonomura , Kyouji Yoshino
IPC分类号： G06F17/17
CPC分类号： G06F7/544
摘要： Interpolation of signed values A and B is efficiently performed by simple circuitry. To calculate an interpolated value C based on a 4-bit values A (bits a3a2a1a0) and B (bits b3b2b1b0) expressing a negative number by twos complement notation and a 4-bit interpolation rate D (bits d3d2d1d0) consisting of only a decimal part, a basic expression of C=(1−D)*A+D*B is transformed into an expression composed of an unsigned part that includes a sum of products with a bit di or a logically inverted value ei of the bit di (i=0, 1, 2, and 3), and indicates an absolute value of the interpolated value C, and a signed part indicating a sign of the interpolated value C. Then, 7 bits of bits c6 through c0 are generated from an arithmetic operation of the unsigned part, and logic judgement of the signed part is performed by considering a carry from the digit of the bit c6 of the arithmetic operation of the unsigned part to generate a bit c7. Significant digits of the obtained 8-bit value (bits c7 through c0) are outputted as an interpolated value.
摘要翻译：符号值A和B的插值由简单的电路有效地执行。为了基于由二进制补码表示负数的4位值A（位a3a2a1a0）和B（位b3b2b1b0）和仅由小数部分组成的4位内插速率D（位d3d2d1d0）计算内插值C ，将C =（1-D）* A + D * B的基本表达式转换成由无符号部分组成的表达式，该无符号部分包括具有位di的乘积之和或位di（i）的逻辑反转值ei = 0,1,2和3），并且表示内插值C的绝对值，以及指示内插值C的符号的有符号部分。然后，从算术运算生成位c6至c0的7位并且通过考虑来自无符号部分的算术运算的位c6的位的进位来执行有符号部分的逻辑判断，以生成位c7。获得的8位值（位c7至c0）的有效数字作为内插值被输出。

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