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1. 发明申请

US20060281283A1 Silicon epitaxial wafer, and silicon epitaxial wafer manufacturing method 审中-公开
标题翻译：硅外延晶片和硅外延晶片制造方法
公开(公告)号：US20060281283A1
公开(公告)日：2006-12-14
申请号：US10556429
申请日：2004-04-02
申请人： Tomosuke Yoshida , Hitoshi Tsunoda , Masahiro Kato
发明人： Tomosuke Yoshida , Hitoshi Tsunoda , Masahiro Kato
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： C30B29/06 , C30B23/02 , C30B25/02
摘要： A silicon epitaxial wafer (W) comprising: a silicon single crystal substrate (1) having a COP (100) on a main surface (11), and a silicon epitaxial layer (2) grown by vapor phase epitaxy on the main surface (11) of the silicon single crystal substrate (1), wherein the main surface (11) is inclined from a (100) plane in a [011] direction or a [0-1-1] direction by an angle θ with respect to a [100] axis as well as inclined from a (100) plane in a [01-1] direction or a [0-11] direction by an angle φ with respect to a [100] axis, and at least one of the angle θ and the angle φ is from 0° to 15′.
摘要翻译：一种硅外延晶片（W），包括：在主表面（11）上具有COP（100）的硅单晶衬底（1）和在主表面（11）上通过气相外延生长的硅外延层（2）），其中所述主表面（11）从[011]方向或[0-1-1]方向上的（100）面倾斜相对于所述硅单晶基板（1）的角度θ 以及从[01-1]方向或[0-11]方向的（100）面倾斜相对于[100]轴的角度φi，并且至少一个角度 θ和角度phi为0°至15'。

2. 发明申请

US20070291537A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20070291537A1
公开(公告)日：2007-12-20
申请号：US11838484
申请日：2007-08-14
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

3. 发明授权

US5718762A Method for vapor-phase growth 失效
标题翻译：气相生长方法
公开(公告)号：US5718762A
公开(公告)日：1998-02-17
申请号：US607566
申请日：1996-02-27
申请人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
发明人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
IPC分类号： C30B29/06 , C23C16/02 , C30B25/02 , C30B33/12 , H01L21/205 , H01L21/302 , H01L21/3065 , C30B25/20
CPC分类号： C30B29/06 , C30B25/02
摘要： A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.
摘要翻译：提供了一种气相生长方法，其允许产生没有微粗糙度的光滑表面的外延膜。该方法包括在低于800℃的温度下开始的惰性气体的氛围中加热硅单晶衬底的步骤，以及去除在硅单晶衬底的表面上形成的自然氧化膜的步骤在气相生长前，在不低于950℃，不高于1190℃的氢气气氛中用氢气蚀刻。

4. 发明授权

US07616507B2 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US07616507B2
公开(公告)日：2009-11-10
申请号：US11838463
申请日：2007-08-14
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.
摘要翻译：一种包括非易失性半导体存储器件和控制器的存储器系统。存储装置包括多个字线; 以及多个存储单元，每个存储单元连接到对应的一条字线，并且每个具有用于存储多值电平的N个阈值电压，其中N是4或更大的自然数; 其中，所述多个存储单元的每一个中存储的数据构成多个页面，至少只有一部分多值级别用于存储数据，数据“1”总是写入下页，“0” 或“1”二进制数据被写入上部页面时，在写入非易失性存储器件时，在每个页面中写入相同的数据，并且只有读取相同数据的页面的一部分才被读取非易失性存储器件。

5. 发明申请

US20070291540A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20070291540A1
公开(公告)日：2007-12-20
申请号：US11838463
申请日：2007-08-14
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.
摘要翻译：非易失性半导体存储器控制器具有多个字线和多个存储单元。每个存储单元连接到相应的一行字线，并且每个存储单元具有N个阈值电压，其中N是4或更大的自然数。多个存储单元构成多个页面，当写入非易失性存储器时，在每个页面中写入相同的数据，并且在读出非易失性存储器时仅访问写入相同数据的页面的一部分。

6. 发明申请

US20060246689A1 Soi wafer and process for producing the same 有权
标题翻译： Soi晶圆和生产过程相同
公开(公告)号：US20060246689A1
公开(公告)日：2006-11-02
申请号：US10554960
申请日：2004-05-07
申请人： Kiyotaka Takano , Hitoshi Tsunoda
发明人： Kiyotaka Takano , Hitoshi Tsunoda
IPC分类号： H01L21/30 , H01L21/46 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/76251 , Y10S65/08 , Y10T117/10
摘要： The present invention provides an SOI wafer having at least an SOI layer, in which a plain orientation of the SOI layer is off-angled from {110} only in a direction to , and an off-angle is from 5 minutes to 2 degrees, and a method of producing an SOI wafer comprising at least bonding a base wafer and a bond wafer consisting of a silicon single crystal, and forming an SOI layer by thinning the bond wafer, wherein the bond wafer is used where a plain orientation thereof is off-angled from {110} only in a direction to , and an off-angle is from 5 minutes to 2 degrees. Thereby, there can be provided an SOI wafer having both high uniformity of film thickness and good micro-roughness to be suitable for fabricating high speed devices, and provided a method of producing the SOI wafer.
摘要翻译：本发明提供了至少具有SOI层的SOI晶片，其中SOI层的平坦取向仅在{110}仅在<100>的方向偏角，偏角为5分钟至以及制造SOI晶片的方法，所述SOI晶片至少包括接合由硅单晶构成的基底晶片和接合晶片，并且通过使所述接合晶片变薄来形成SOI层，其中所述接合晶片用于平坦取向其从{110}仅在<100>的方向偏角，偏角为5分钟至2度。由此，可以提供具有均匀性均匀的膜厚和良好的微粗糙度的SOI晶片，以适合于制造高速器件，并提供了制造SOI晶片的方法。

7. 发明申请

US20100199082A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20100199082A1
公开(公告)日：2010-08-05
申请号：US12756836
申请日：2010-04-08
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

8. 发明授权

US07357839B2 SOI wafer and a method of producing the same 有权
标题翻译： SOI晶片及其制造方法
公开(公告)号：US07357839B2
公开(公告)日：2008-04-15
申请号：US10554960
申请日：2004-05-07
申请人： Kiyotaka Takano , Hitoshi Tsunoda
发明人： Kiyotaka Takano , Hitoshi Tsunoda
IPC分类号： C30B35/00 , C03C27/02
CPC分类号： H01L21/76251 , Y10S65/08 , Y10T117/10
摘要： The present invention provides an SOI wafer having at least an SOI layer, in which a plain orientation of the SOI layer is off-angled from {110} only in a direction to , and an off-angle is from 5 minutes to 2 degrees, and a method of producing an SOI wafer comprising at least bonding a base wafer and a bond wafer consisting of a silicon single crystal, and forming an SOI layer by thinning the bond wafer, wherein the bond wafer is used where a plain orientation thereof is off-angled from {110} only in a direction to , and an off-angle is from 5 minutes to 2 degrees. Thereby, there can be provided an SOI wafer having both high uniformity of film thickness and good micro-roughness to be suitable for fabricating high speed devices, and provided a method of producing the SOI wafer.
摘要翻译：本发明提供了至少具有SOI层的SOI晶片，其中SOI层的平坦取向仅在{110}仅在<100>的方向偏角，偏角为5分钟至以及制造SOI晶片的方法，所述SOI晶片至少包括接合由硅单晶构成的基底晶片和接合晶片，并且通过使所述接合晶片变薄来形成SOI层，其中所述接合晶片用于平坦取向其从{110}仅在<100>的方向偏角，偏角为5分钟至2度。由此，可以提供具有均匀性均匀的膜厚和良好的微粗糙度的SOI晶片，以适合于制造高速器件，并提供了制造SOI晶片的方法。

9. 发明申请

US20050223211A1 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20050223211A1
公开(公告)日：2005-10-06
申请号：US11084039
申请日：2005-03-21
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F11/10 , G06F9/00 , G06F9/445 , G06F12/00 , G06F12/02
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： The present invention enables a CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of avarage system boot-up time. The present invention is a processor boot-up controller that includes: volatile memory, which is connected to nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory which is configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit; is connected to the external CPU and the nonvolatile memory, and boot-up controls the CPU by reading data from the nonvolatile memory. The present invention is an information processing system using a controller for nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.
摘要翻译：本发明使得CPU能够在SRAM的就绪定时同步的最短时间内访问SRAM，从而减少了系统启动时间。本发明是一种处理器启动控制器，其包括：易失性存储器，其连接到非易失性存储器; 选择器，其将启动代码从非易失性存储器传送到易失性存储器; 用于非易失性存储器的控制器，其由引导控制定序器配置，其将CPU读入数据发送到CPU并使CPU进入等待状态，直到引导代码传送完成; 和错误检测和校正单元; 连接到外部CPU和非易失性存储器，并通过从非易失性存储器读取数据启动控制CPU。本发明是使用非易失性存储器的控制器，微处理器启动控制器和多值非易失性存储器的信息处理系统。

10. 发明授权

US08171281B2 Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device 有权
标题翻译：微处理器引导控制器连接到处理器和NAND闪存，用于控制计算机设备的启动
公开(公告)号：US08171281B2
公开(公告)日：2012-05-01
申请号：US12756836
申请日：2010-04-08
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

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