专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070291537A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20070291537A1
公开(公告)日：2007-12-20
申请号：US11838484
申请日：2007-08-14
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

2. 发明申请

US20100199082A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20100199082A1
公开(公告)日：2010-08-05
申请号：US12756836
申请日：2010-04-08
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

3. 发明申请

US20050223211A1 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20050223211A1
公开(公告)日：2005-10-06
申请号：US11084039
申请日：2005-03-21
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F11/10 , G06F9/00 , G06F9/445 , G06F12/00 , G06F12/02
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： The present invention enables a CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of avarage system boot-up time. The present invention is a processor boot-up controller that includes: volatile memory, which is connected to nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory which is configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit; is connected to the external CPU and the nonvolatile memory, and boot-up controls the CPU by reading data from the nonvolatile memory. The present invention is an information processing system using a controller for nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.
摘要翻译：本发明使得CPU能够在SRAM的就绪定时同步的最短时间内访问SRAM，从而减少了系统启动时间。本发明是一种处理器启动控制器，其包括：易失性存储器，其连接到非易失性存储器; 选择器，其将启动代码从非易失性存储器传送到易失性存储器; 用于非易失性存储器的控制器，其由引导控制定序器配置，其将CPU读入数据发送到CPU并使CPU进入等待状态，直到引导代码传送完成; 和错误检测和校正单元; 连接到外部CPU和非易失性存储器，并通过从非易失性存储器读取数据启动控制CPU。本发明是使用非易失性存储器的控制器，微处理器启动控制器和多值非易失性存储器的信息处理系统。

4. 发明授权

US07616507B2 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US07616507B2
公开(公告)日：2009-11-10
申请号：US11838463
申请日：2007-08-14
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.
摘要翻译：一种包括非易失性半导体存储器件和控制器的存储器系统。存储装置包括多个字线; 以及多个存储单元，每个存储单元连接到对应的一条字线，并且每个具有用于存储多值电平的N个阈值电压，其中N是4或更大的自然数; 其中，所述多个存储单元的每一个中存储的数据构成多个页面，至少只有一部分多值级别用于存储数据，数据“1”总是写入下页，“0” 或“1”二进制数据被写入上部页面时，在写入非易失性存储器件时，在每个页面中写入相同的数据，并且只有读取相同数据的页面的一部分才被读取非易失性存储器件。

5. 发明申请

US20070291540A1 MICROPROCESSOR BOOT-UP CONTROLLER, NONVOLATILE MEMORY CONTROLLER, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US20070291540A1
公开(公告)日：2007-12-20
申请号：US11838463
申请日：2007-08-14
申请人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi SUKEGAWA , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.
摘要翻译：非易失性半导体存储器控制器具有多个字线和多个存储单元。每个存储单元连接到相应的一行字线，并且每个存储单元具有N个阈值电压，其中N是4或更大的自然数。多个存储单元构成多个页面，当写入非易失性存储器时，在每个页面中写入相同的数据，并且在读出非易失性存储器时仅访问写入相同数据的页面的一部分。

6. 发明授权

US08171281B2 Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device 有权
标题翻译：微处理器引导控制器连接到处理器和NAND闪存，用于控制计算机设备的启动
公开(公告)号：US08171281B2
公开(公告)日：2012-05-01
申请号：US12756836
申请日：2010-04-08
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

7. 发明授权

US07725706B2 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US07725706B2
公开(公告)日：2010-05-25
申请号：US11838484
申请日：2007-08-14
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/00 , G11C8/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
摘要翻译：信息处理装置具有多值NAND非易失性存储器，包括多个字线和连接到各个字线的多个存储单元。每个存储单元具有多个阈值电压，并被分成第一和第二存储区域。程序代码被存储在第一存储区域中，并且用户数据被存储在第二存储区域中。该装置还包括从多值NAND非易失性存储器传送程序代码的易失性存储器。该装置还包括连接到易失性存储器并被配置为基于传送到易失性存储器的程序代码进行操作的CPU。

8. 发明授权

US07516371B2 ECC control apparatus 有权
标题翻译： ECC控制装置
公开(公告)号：US07516371B2
公开(公告)日：2009-04-07
申请号：US10787183
申请日：2004-02-27
申请人： Kenji Sakaue , Hiroshi Sukegawa , Hitoshi Tsunoda
发明人： Kenji Sakaue , Hiroshi Sukegawa , Hitoshi Tsunoda
IPC分类号： G06F11/00
CPC分类号： G06F11/1068
摘要： An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.
摘要翻译： ECC控制装置连接在主机和存储器之间。该装置包括第一输入/输出电路，检测电路，代码生成电路，代码插入电路，第二输入/输出电路。第一个输入/输出电路向主机输入和输出数据。检测电路检测保护数据区域和输入到第一输入/输出电路并具有预定数据长度的写入数据的冗余区域。代码生成电路生成用于校正存储在保护数据区域中的数据中的错误的纠错码。代码插入电路将纠错码插入冗余区域。第二个输入/输出电路输入和输出数据往返于存储器。

9. 发明授权

US07464259B2 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
标题翻译：微处理器启动控制器，非易失性存储器控制器和信息处理系统
公开(公告)号：US07464259B2
公开(公告)日：2008-12-09
申请号：US11084039
申请日：2005-03-21
申请人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
发明人： Hiroshi Sukegawa , Kenji Sakaue , Hitoshi Tsunoda
IPC分类号： G06F9/00
CPC分类号： G11C11/5642 , G06F9/4403 , G11C16/0483 , G11C16/20 , G11C29/74 , G11C2211/5641
摘要： A processor boot-up controller includes: a volatile memory connected to a nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit connected to the external CPU and the nonvolatile memory. The processor boot-up controls the CPU by reading data from the nonvolatile memory. The processor enables the CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of average system boot-up time. An information processing system can use the controller for example for a nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.
摘要翻译：处理器启动控制器包括：连接到非易失性存储器的易失性存储器; 选择器，其将启动代码从非易失性存储器传送到易失性存储器; 由启动控制定序器配置的用于非易失性存储器的控制器，其将CPU读入数据发送到CPU并使CPU进入等待状态，直到引导代码传送完成; 以及连接到外部CPU和非易失性存储器的错误检测和校正单元。处理器启动通过从非易失性存储器读取数据来控制CPU。处理器使CPU能够在最短时间内与SRAM的就绪时序同步访问SRAM，导致平均系统启动时间减少。信息处理系统可以使用例如用于非易失性存储器，微处理器启动控制器和多值非易失性存储器的控制器。

10. 发明授权

US5718762A Method for vapor-phase growth 失效
标题翻译：气相生长方法
公开(公告)号：US5718762A
公开(公告)日：1998-02-17
申请号：US607566
申请日：1996-02-27
申请人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
发明人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
IPC分类号： C30B29/06 , C23C16/02 , C30B25/02 , C30B33/12 , H01L21/205 , H01L21/302 , H01L21/3065 , C30B25/20
CPC分类号： C30B29/06 , C30B25/02
摘要： A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.
摘要翻译：提供了一种气相生长方法，其允许产生没有微粗糙度的光滑表面的外延膜。该方法包括在低于800℃的温度下开始的惰性气体的氛围中加热硅单晶衬底的步骤，以及去除在硅单晶衬底的表面上形成的自然氧化膜的步骤在气相生长前，在不低于950℃，不高于1190℃的氢气气氛中用氢气蚀刻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式