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1. 发明申请

US20050031312A1 Method and apparatus for signal reproduction 审中-公开
标题翻译：用于信号再现的方法和装置
公开(公告)号：US20050031312A1
公开(公告)日：2005-02-10
申请号：US10895377
申请日：2004-07-21
申请人： Tomoko Matsui , Ryouji Yamaguchi , Tadashi Shibata
发明人： Tomoko Matsui , Ryouji Yamaguchi , Tadashi Shibata
IPC分类号： G11B20/10 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/804 , H04N9/806 , H04N5/76
CPC分类号： H04N9/8063 , G11B20/10 , G11B2020/1062 , G11B2020/10694 , G11B2020/10814 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/8042 , H04N9/8047
摘要： This invention provides a method and apparatus for signal reproduction that can simultaneously reproduce N (N≧2) signals which are previously multiplexed, and simultaneously reproduce N independent signals. This apparatus selectively inputs the independent N coded signals in time division, adds the corresponding stream information to the selected input signal among N kinds of stream information for identifying the input signals, detects the stream information from the respective input signal, decodes the respective input signal by a decoding method corresponding to the respective input signal, which is decided based on the detected stream information, and outputs the decoded signal.
摘要翻译：本发明提供一种用于信号再现的方法和装置，其可以同时再现先前多路复用的N（N> = 2）个信号，同时再现N个独立信号。该装置以时分方式选择性地输入独立的N个编码信号，将N个用于识别输入信号的流信息中的所选输入信号相加的流信息相加，从相应的输入信号检测流信息，解码各输入信号通过与基于检测到的流信息决定的各个输入信号对应的解码方式，输出解码信号。

2. 发明授权

US06949478B2 Oxide film forming method 失效
标题翻译：氧化膜成型方法
公开(公告)号：US06949478B2
公开(公告)日：2005-09-27
申请号：US10120628
申请日：2002-04-11
申请人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
发明人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66 , H01L21/31
CPC分类号： C30B23/02 , C23C8/10 , C23C8/36 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.
摘要翻译：使用带电粒子在超清洁环境下进行形成具有高绝缘性的氧化膜的方法。

3. 发明授权

US06606119B1 Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US06606119B1
公开(公告)日：2003-08-12
申请号：US09039126
申请日：1998-03-13
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： H04N5208
CPC分类号： H04N5/357 , H04N5/142
摘要： The present invention has as an object thereof to provide a semiconductor arithmetic circuit which is capable of conducting edge accentuation processing, edge detection processing, and noise removal by means of averaging processing of an image, using extremely simple circuitry. A semiconductor arithmetic circuit is provided with an amplifier circuit in which an input terminal is connected to the gate electrode of at least one MOS type transistor, a first signal input terminal, which is connected with the input terminal via a first switching element, and a plurality of second signal input terminals, which are connected with the input terminal via a capacity element; wherein a mechanism is provided for opening the first switching element in a state in which a first signal voltage is applied to the input terminal and a predetermined second input signal voltage group is applied to the second signal input terminals, and for thereafter applying a predetermined third input signal voltage group to the second signal input terminals, and wherein the amplifier circuit comprises a source follower circuit or a voltage follower circuit.
摘要翻译：本发明的目的是提供一种半导体运算电路，其能够通过使用非常简单的电路的图像的平均处理来进行边缘突出处理，边缘检测处理和噪声去除。半导体运算电路设置有放大电路，其中输入端连接到至少一个MOS型晶体管的栅电极，经由第一开关元件与输入端连接的第一信号输入端和多个第二信号输入端，经由电容元件与输入端连接; 其特征在于，提供一种机构，用于在将第一信号电压施加到输入端子并且将预定的第二输入信号电压组施加到第二信号输入端子的状态下打开第一开关元件，然后施加预定的第三输入信号电压组到第二信号输入端，并且其中放大器电路包括源极跟随器电路或电压跟随器电路。

4. 发明授权

US5937399A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5937399A
公开(公告)日：1999-08-10
申请号：US663248
申请日：1996-06-11
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F15/18 , G06N3/063 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit includes one or more neuron MOS transistors on a substrate. The MOS transistor comprises a semiconductor region of one conductivity type, source and drain regions of opposite conductivity type disposed in this region, floating gate disposed on an insulating film between the source and drain regions, and a plurality of input coupling electrodes making capacitive coupling with the floating gate through the insulating film, wherein the floating gate is connected to at least one switching device.
摘要翻译： PCT No.PCT / JP94 / 02001 Sec。 371日期：1996年6月11日 102（e）日期1996年6月11日PCT 1994年11月29日PCT公布。第WO95 / 15581号公报日期：1995年6月8日半导体集成电路在衬底上包括一个或多个神经元MOS晶体管。 MOS晶体管包括一个导电类型的半导体区域，设置在该区域中的具有相反导电类型的源极和漏极区域，浮置栅极设置在源极和漏极区域之间的绝缘膜上，以及多个输入耦合电极，所述浮栅通过所述绝缘膜，其中所述浮动栅极连接到至少一个开关装置。

5. 发明授权

US5818081A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5818081A
公开(公告)日：1998-10-06
申请号：US656288
申请日：1996-07-01
申请人： Tadahiro Ohmi , Tadashi Shibata , Hideo Kosaka , Takeo Yamashita
发明人： Tadahiro Ohmi , Tadashi Shibata , Hideo Kosaka , Takeo Yamashita
IPC分类号： G06G7/60 , G06N3/063 , G11C27/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C27/005 , G06N3/063 , G06N3/0635 , H01L29/42324 , H01L29/7881
摘要： Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished. The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.
摘要翻译： PCT No.PCT / JP94 / 02000 Sec。 371日期：1996年7月1日 102（e）日期1996年7月1日PCT 1994年11月29日PCT PCT。公开号WO95 / 15580 日期1995年6月8日可以在低功率半导体器件中由较少数量的元件形成，这实现了高度集成的神经网络。突触加权的精确修改成为可能，并且可以实现具有实用水平的神经元计算机芯片。半导体器件包括用于电荷注入的第一电极，通过第一绝缘膜连接到浮置栅极; 用于施加通过第二绝缘膜连接到浮置栅极的编程脉冲的第二电极和使用浮置栅极作为其栅电极的MOS晶体管，其中从MOS晶体管的源极提供的电荷将第一电极到由浮置栅极的电位确定的预定值，并且通过对第二电极施加预定的脉动电压，电荷通过第一绝缘膜在浮置栅极和第一电极之间传递。

6. 发明授权

US5789985A Frequency multiplying device and digitally-controlled oscillator 失效
标题翻译：倍频装置和数字控制振荡器
公开(公告)号：US5789985A
公开(公告)日：1998-08-04
申请号：US621607
申请日：1996-03-22
申请人： Shigenori Yamauchi , Takamoto Watanabe , Tadashi Shibata , Yoshinori Fujihashi
发明人： Shigenori Yamauchi , Takamoto Watanabe , Tadashi Shibata , Yoshinori Fujihashi
IPC分类号： H03K5/00 , H03K3/03 , H03L7/099 , H03B27/00 , H03K5/26 , H03L7/06
CPC分类号： H03L7/0991
摘要： A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference signal PREF multiplied by sixteen (32/2) is generated by the digital oscillation circuit.
摘要翻译：将外部提供的参考信号PREF的频率相乘的倍频装置包括数字控制的振荡电路，其包括由环形配置中的三十二个反相电路形成的环形振荡器，该环形振荡器适于产生十六个时钟信号，周期，是每个反相电路的反相时间的三十二倍，是反相电路反相时间的两倍的相位间隔，并产生具有与频率控制数据CD相对应的周期的输出信号POUT，该周期以相位差的分辨率时钟信号的时间;计数器/数据锁存电路，用于对参考信号PREF的一个周期内由环形振荡器释放的时钟信号RCK进行计数，并将计数值的频率控制数据CD传送到数字振荡电路;以及控制电路，其控制电路的运行，使得具有频率的振荡输出信号POUT 通过数字振荡电路产生参考信号PREF乘以十六（32/2）的通量。

7. 发明授权

US5745416A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5745416A
公开(公告)日：1998-04-28
申请号：US581740
申请日：1995-12-29
申请人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
发明人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C27/00 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/045 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/0441 , G11C16/0458 , G11C27/005 , G11C2211/5612 , G11C2211/5613
摘要： A non-volatile semiconductor memory which is capable of high speed and highly accurate analog data writing. The memory includes a first MOS type transistor having a first floating gate which is electrically isolated. A first electrode is capacitively coupled with the first floating gate. A second electrode is connected via a tunnel junction with the first floating gate. A third electrode is capacitively coupled with the second electrode. A second MOS type transistor interconnects the first and second electrodes. A means is provided for applying a predetermined potential difference between the first and third electrodes to thereby cause a tunnel current to flow in the tunnel junction and to store an electric charge in the first floating gate to thereby cause the second MOS type transistor to conduct when the electric charge has reached a predetermined value.
摘要翻译：一种能够进行高速和高精度模拟数据写入的非易失性半导体存储器。存储器包括具有电隔离的第一浮动栅极的第一MOS型晶体管。第一电极与第一浮栅电容耦合。第二电极经由与第一浮动栅极的隧道结连接。第三电极与第二电极电容耦合。第二MOS型晶体管互连第一和第二电极。提供了一种用于在第一和第三电极之间施加预定电位差从而使隧道电流在隧道结中流动并在第一浮栅中存储电荷从而使第二MOS型晶体管导通的装置，电荷已经达到预定值。

8. 发明授权

US5728278A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US5728278A
公开(公告)日：1998-03-17
申请号：US340472
申请日：1994-11-14
申请人： Nobuyuki Okamura , Atsushi Yamagami , Tadahiro Ohmi , Haruhiro Harry Goto , Tadashi Shibata
发明人： Nobuyuki Okamura , Atsushi Yamagami , Tadahiro Ohmi , Haruhiro Harry Goto , Tadashi Shibata
IPC分类号： C23C14/34 , C23C14/00 , C23C14/35 , C23C14/56 , C23C16/509 , H01J37/34 , H01L21/203
CPC分类号： C23C14/35 , C23C14/564 , H01J37/3244 , H01J37/3402
摘要： A plasma processing apparatus has a vacuum container which contains a pair of electrodes for causing a discharge for generating a plasma, and a shielding plate for separating a plasma processing region including a space between the electrodes from a region in contact with the inner wall of the vacuum container in such a manner that both the regions communicate with each other. The apparatus includes a means for causing a pressure difference between the plasma processing region and the region in contact with the inner wall of the vacuum container.
摘要翻译：等离子体处理装置具有真空容器，该真空容器包含用于产生等离子体的放电的一对电极，以及用于将包括电极之间的空间的等离子体处理区域从与所述等离子体的内壁接触的区域分离的屏蔽板真空容器以两个区域彼此连通的方式。该装置包括用于引起等离子体处理区域和与真空容器的内壁接触的区域之间的压力差的装置。

9. 发明授权

US5706403A Semiconductor neural circuit device 失效
标题翻译：半导体神经电路器件
公开(公告)号：US5706403A
公开(公告)日：1998-01-06
申请号：US424267
申请日：1995-04-24
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , G06N99/00 , H01L21/822 , H01L27/04 , H01L29/78
CPC分类号： G06N3/0635
摘要： A semiconductor neural circuit device having a very simple circuit and a self-teaching function, by which a neural network is allowed to learn. The device comprises synapse circuits which output weighted values, and neuron circuits which execute linear addition of the output signals from the synapse circuits, and output the signal voltages of high and low levels with respect to a given threshold value V.sub.TH. In the case of learning of increasing the total value Z, only when V.sub.TH -.epsilon.
摘要翻译： PCT No.PCT / JP93 / 01573 Sec。 371日期1995年04月24日 102（e）1995年4月24日PCT PCT 1993年10月29日PCT公布。 WO94 / 10648 PCT公开日期1994年5月11日一种具有非常简单的电路和自我教学功能的半导体神经电路器件，通过该功能允许神经网络学习。该装置包括输出加权值的突触电路和执行来自突触电路的输出信号的线性相加的神经元电路，并且相对于给定的阈值VTH输出高电平和低电平的信号电压。在学习增加总值Z的情况下，只有当相对于两个正参数ε和α的VTH-ε

10. 发明授权

US5550200A Method of producing conjugated diene-aromatic vinyl hydrocarbon copolymers 失效
标题翻译：共轭二烯 - 芳族乙烯基烃共聚物的制备方法
公开(公告)号：US5550200A
公开(公告)日：1996-08-27
申请号：US478526
申请日：1995-06-07
申请人： Tadashi Shibata , Ryota Fujio
发明人： Tadashi Shibata , Ryota Fujio
IPC分类号： C08F2/44 , C08F2/38 , C08F4/00 , C08F4/42 , C08F4/46 , C08F4/48 , C08F236/10 , C08K3/04 , C08K5/01 , C08L9/00 , C08L9/06 , C08L21/00 , C08F4/56
CPC分类号： C08F236/10 , C08L9/06 , C08K3/04
摘要： A rubber composition, having good breaking properties, high tan.delta., good wear resistance and a method for preparing a copolymer used in the rubber composition. The copolymer is a butadiene-styrene copolymer prepared in the presence of an organopotassium compound, an oxolanyl alkane and an organolithium initiator compound. The copolymer may be modified. A vulcanite of the rubber composition including 20 parts or more of the copolymer of the present invention has good properties.
摘要翻译：一种橡胶组合物，具有良好的断裂性，高的tanδ，良好的耐磨性和用于橡胶组合物中使用的共聚物的制备方法。共聚物是在有机钾化合物，氧杂环丁烷基烷烃和有机锂引发剂化合物存在下制备的丁二烯 - 苯乙烯共聚物。可以改性共聚物。包含20份或更多份本发明共聚物的橡胶组合物的硫化胶具有良好的性能。

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