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1. 发明授权

US06459312B2 Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop 失效
标题翻译：半导体集成电路，具有相同电路的延迟锁定环路，自同步管线型系统，压控振荡器和锁相环
公开(公告)号：US06459312B2
公开(公告)日：2002-10-01
申请号：US09919926
申请日：2001-08-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： H03L700
CPC分类号： H03K3/0315 , H03K3/354 , H03K5/133 , H03K2005/00045 , H03L7/0812 , H03L7/0995 , H03L2207/06
摘要： The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.
摘要翻译：通过其中信号输入端子通过第一电容器连接到读出放大器的输入端的电路来解决抖动量增加与延迟量增加的问题，控制输入端子通过第二电容器连接到输入端读出放大器的端子和读出放大器的输入端与第一和第二电容器之间的公共连接点是浮动节点，并且其中通过信号输入端施加到读出放大器的输入端的信号是垂直的至少在感测放大器的判定阈值附近，施加到控制输入端子的控制信号移位，从而控制输出的延迟量。

2. 发明授权

US6127852A Semiconductor integrated circuit for parallel signal processing 失效
标题翻译：半导体集成电路并行信号处理
公开(公告)号：US6127852A
公开(公告)日：2000-10-03
申请号：US110014
申请日：1998-07-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： G01D1/12 , G06G7/12 , G06G7/122 , H01L21/8238 , H01L27/092 , H01L29/78 , H03D1/00
CPC分类号： G06G7/122
摘要： To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.
摘要翻译：为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号，通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元，栅极和第一电容装置连接到第二电容装置的一个端子侧，以及控制装置，用于使第二电容装置的另一个端子侧的电压波动，以进一步增加或减少对应于在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少，多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源，并且执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测通过第二电容装置的另一个端子侧的电压。

3. 发明授权

US6115725A Semiconductor arithmetic apparatus 失效
标题翻译：半导体运算装置
公开(公告)号：US6115725A
公开(公告)日：2000-09-05
申请号：US14644
申请日：1998-01-28
申请人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
发明人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
IPC分类号： G06T9/00 , H03M7/30 , G06F7/00 , H04N7/12
CPC分类号： H03M7/3082 , G06T9/008 , H04N19/94
摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.
摘要翻译：使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路（210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出，将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

4. 发明授权

US5939925A Semiconductor circuitry to process analog signals using weighted- sum operations 失效
标题翻译：半导体电路，用加权和运算处理模拟信号
公开(公告)号：US5939925A
公开(公告)日：1999-08-17
申请号：US930508
申请日：1997-11-07
申请人： Tadashi Shibata , Tadahiro Ohmi , Ning Mei Yu , Tsutomu Nakai
发明人： Tadashi Shibata , Tadahiro Ohmi , Ning Mei Yu , Tsutomu Nakai
IPC分类号： G06F17/16 , G06J1/00 , G06K9/64 , G06G7/12
CPC分类号： G06K9/64 , G06F17/16 , G06J1/00
摘要： A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.
摘要翻译： PCT No.PCT / JP96 / 00883 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。出版物WO96 / 30827 日期1996年10月3日半导体运算电路进行实时模拟矢量运算，以确定移动物体的图像的重心。电路采用利用CMOS源极跟随器电路的第一处理级，对模拟信号执行加权线性和运算。第二处理阶段利用比较器电路执行涉及来自加权和和非加权和运算的数据的比较运算。第三处理级利用异或门来提供基于比较运算结果的数字数据输出。

5. 发明授权

US5683072A Thin film forming equipment 失效
标题翻译：薄膜成型设备
公开(公告)号：US5683072A
公开(公告)日：1997-11-04
申请号：US508405
申请日：1995-07-31
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C8/14 , C23C14/34 , C23C14/35 , C23C14/56 , C23C16/44 , F16K31/02 , F16K51/02 , H01J37/32 , F16K3/18
CPC分类号： H01J37/32174 , C23C14/34 , C23C14/35 , C23C14/56 , C23C14/564 , C23C16/4404 , C23C8/14 , F16K31/02 , F16K51/02 , H01J37/32082 , H01J2237/186
摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.
摘要翻译：一种用于薄膜形成装置的闸阀。闸阀包括两个相邻的低压室和分隔两个室的壁。该壁包括孔和用于覆盖孔的薄板。薄板可以在基本上平行于板表面的方向上移动。闸阀还包括用于在薄板和壁之间施加直流电的电压源。

6. 发明授权

US5362672A Method of forming a monocrystalline film having a closed loop step portion on the substrate 失效
标题翻译：在基板上形成具有闭环台阶部分的单晶膜的方法
公开(公告)号：US5362672A
公开(公告)日：1994-11-08
申请号：US465175
申请日：1990-02-01
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C14/06 , H01L21/20 , H01L21/203 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/0242 , H01L21/02422 , H01L21/02491 , H01L21/02532 , H01L21/02631 , H01L21/84 , Y10S148/158
摘要： A method of manufacturing a semiconductor device, and particularly a method of forming a monocrystalline film on a substrate. The method includes the step of forming a conductor layer having a step portion on the surface of a substrate. The step portion includes a lateral face which surrounds the lower surface of the step portion to form a closed loop. After the conductor layer has been formed on the surface of the substrate, a monocrystalline film is formed directly on the substrate. Specifically, the film is formed on the lower surface of the step portion, while a DC potential is applied to the conductor layer.
摘要翻译： PCT No.PCT / JP89 / 00599 Sec。 371日期1990年2月1日 102（e）1990年2月1日PCT PCT。1989年6月15日PCT公布。公开号WO89 / 12908 日期：1989年12月28日。一种制造半导体器件的方法，特别是在衬底上形成单晶膜的方法。该方法包括在衬底的表面上形成具有台阶部分的导体层的步骤。台阶部分包括侧面，该侧面围绕台阶部分的下表面以形成闭环。在衬底表面上形成导体层之后，直接在衬底上形成单晶膜。具体地，在台阶部的下表面上形成膜，同时对导体层施加DC电位。

7. 发明授权

US5258657A Neuron circuit 失效
标题翻译：神经元电路
公开(公告)号：US5258657A
公开(公告)日：1993-11-02
申请号：US777352
申请日：1992-01-06
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G06G7/60 , G06F15/18 , G06N3/063 , G06N99/00 , H01L21/8234 , H01L27/088 , H01L27/115 , H01L29/66 , H01L29/788 , H03K19/08 , H03K19/23
CPC分类号： G06N3/0635 , H01L27/115 , H01L29/7881 , H01L2924/0002
摘要： A semiconductor device of this invention comprises on a substrate a first semiconductor region of one conductive type, first source and drain regions of the opposite conductive type formed in said semiconductor region, a first gate electrode formed in a region separating said source and drain regions, the first gate electrode being electrically floating through an insulating film, and at least two second gate electrodes connected to said first gate electrode by capacitive coupling, wherein an inversion layer is formed under said first gate electrode and said first source and drain regions are electrically connected together only when a predetermined threshold value is exceeded by the absolute value of a value obtained by linearly summing up the weighted voltages applied to said second gate electrodes.

8. 发明授权

US06949478B2 Oxide film forming method 失效
标题翻译：氧化膜成型方法
公开(公告)号：US06949478B2
公开(公告)日：2005-09-27
申请号：US10120628
申请日：2002-04-11
申请人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
发明人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66 , H01L21/31
CPC分类号： C30B23/02 , C23C8/10 , C23C8/36 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.
摘要翻译：使用带电粒子在超清洁环境下进行形成具有高绝缘性的氧化膜的方法。

9. 发明授权

US06606119B1 Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US06606119B1
公开(公告)日：2003-08-12
申请号：US09039126
申请日：1998-03-13
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： H04N5208
CPC分类号： H04N5/357 , H04N5/142
摘要： The present invention has as an object thereof to provide a semiconductor arithmetic circuit which is capable of conducting edge accentuation processing, edge detection processing, and noise removal by means of averaging processing of an image, using extremely simple circuitry. A semiconductor arithmetic circuit is provided with an amplifier circuit in which an input terminal is connected to the gate electrode of at least one MOS type transistor, a first signal input terminal, which is connected with the input terminal via a first switching element, and a plurality of second signal input terminals, which are connected with the input terminal via a capacity element; wherein a mechanism is provided for opening the first switching element in a state in which a first signal voltage is applied to the input terminal and a predetermined second input signal voltage group is applied to the second signal input terminals, and for thereafter applying a predetermined third input signal voltage group to the second signal input terminals, and wherein the amplifier circuit comprises a source follower circuit or a voltage follower circuit.
摘要翻译：本发明的目的是提供一种半导体运算电路，其能够通过使用非常简单的电路的图像的平均处理来进行边缘突出处理，边缘检测处理和噪声去除。半导体运算电路设置有放大电路，其中输入端连接到至少一个MOS型晶体管的栅电极，经由第一开关元件与输入端连接的第一信号输入端和多个第二信号输入端，经由电容元件与输入端连接; 其特征在于，提供一种机构，用于在将第一信号电压施加到输入端子并且将预定的第二输入信号电压组施加到第二信号输入端子的状态下打开第一开关元件，然后施加预定的第三输入信号电压组到第二信号输入端，并且其中放大器电路包括源极跟随器电路或电压跟随器电路。

10. 发明授权

US5937399A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5937399A
公开(公告)日：1999-08-10
申请号：US663248
申请日：1996-06-11
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F15/18 , G06N3/063 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit includes one or more neuron MOS transistors on a substrate. The MOS transistor comprises a semiconductor region of one conductivity type, source and drain regions of opposite conductivity type disposed in this region, floating gate disposed on an insulating film between the source and drain regions, and a plurality of input coupling electrodes making capacitive coupling with the floating gate through the insulating film, wherein the floating gate is connected to at least one switching device.
摘要翻译： PCT No.PCT / JP94 / 02001 Sec。 371日期：1996年6月11日 102（e）日期1996年6月11日PCT 1994年11月29日PCT公布。第WO95 / 15581号公报日期：1995年6月8日半导体集成电路在衬底上包括一个或多个神经元MOS晶体管。 MOS晶体管包括一个导电类型的半导体区域，设置在该区域中的具有相反导电类型的源极和漏极区域，浮置栅极设置在源极和漏极区域之间的绝缘膜上，以及多个输入耦合电极，所述浮栅通过所述绝缘膜，其中所述浮动栅极连接到至少一个开关装置。

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