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1. 发明授权

US5686853A Driver circuitry adjusted to allow high speed driving and reduce potential variations of interconnections 失效
标题翻译：驱动电路被调整以允许高速驱动并减少互连的潜在变化
公开(公告)号：US5686853A
公开(公告)日：1997-11-11
申请号：US580485
申请日：1995-12-29
申请人： Tomofumi Iima , Masakazu Yamashina , Masayuki Mizuno
发明人： Tomofumi Iima , Masakazu Yamashina , Masayuki Mizuno
IPC分类号： H03K17/04 , H03K17/687 , H03K19/017 , H03K19/20
CPC分类号： H03K19/01707
摘要： The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage. The first control circuit is adjusted to shift the first output signal between the high and low levels within an initial period of the first time period and then keep the first output signal at the shifted one of the low and high levels until after the first time period expired. The second control circuit is coupled to the input terminal for receiving the input signal. The second control circuit is also coupled to the second output terminal for outputting a second output signal of binary digits via the second output terminal. The second control circuit is biased between the high voltage line and the low voltage line. The second control circuit is adjusted to keep the second output signal at one level of the low and high levels at least until the time approaches the termination of the first time period and then shift the second output signal from the one level to another level within a second time period which is short as the initial period of the first time period.
摘要翻译：本发明提供了一种驱动器电路，其具有用于接收由高电平和低电平组成的二进制数字的输入信号的单个输入端以及至少第一和第二输出端，其中输入信号在第一时间段内几乎线性地变化，因此为了在高电平和低电平之间移动，驱动器电路包括第一和第二控制电路。第一控制电路耦合到输入端以接收输入信号。第一控制电路还耦合到第一输出端子，用于经由第一输出端子输出二进制数字的第一输出信号。第一控制电路在提供高电平的高压线路和提供低电平的低电压线路之间被偏置。调整第一控制电路以在第一时间周期的初始时段内将高电平和低电平之间的第一输出信号移位，然后将第一输出信号保持在低电平和高电平中的移位的一个，直到第一时间段已过期第二控制电路耦合到输入端以接收输入信号。第二控制电路还耦合到第二输出端子，用于经由第二输出端子输出二进制数字的第二输出信号。第二控制电路在高电压线路和低电压线路之间被偏置。调整第二控制电路以将第二输出信号保持在低电平和高电平的一个电平，至少直到时间接近第一时间段的终止，然后将第二输出信号从一个电平移位到另一个电平内作为第一时间段的初始期间的第二时间段。

2. 发明授权

US06229360B1 High speed synchronization circuit in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的高速同步电路
公开(公告)号：US06229360B1
公开(公告)日：2001-05-08
申请号：US09149282
申请日：1998-09-09
申请人： Masayuki Mizuno , Masakazu Yamashina
发明人： Masayuki Mizuno , Masakazu Yamashina
IPC分类号： H03K504
CPC分类号： H03K5/135 , G06F1/10 , H03K5/1252
摘要： A first latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of one direction of a clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, and a second latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of the other direction of the clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, are provided. A desired logic circuit is connected between the first and second latching circuits. By synchronously operating the first and second latching circuits by supplying a common clock signal, a clock synchronization circuit not influenced by fluctuation of the device, fluctuation of temperature or power source can be formed.
摘要翻译：第一锁存电路响应于输入到时钟端子的时钟信号的一个方向的电平转变定时将输入信号从输入端子传送到输出端子一段预定的周期，并且将输出端子的信号状态保持在以及第二锁存电路，响应于输入到时钟端子的时钟信号的另一个方向的电平转换定时，将输入信号从输入端子输出到输出端子一段预定时间段，并且保持信号提供了剩余时段的输出端子的状态。期望的逻辑电路连接在第一和第二锁存电路之间。通过提供公共时钟信号来同步操作第一和第二锁存电路，可以形成不受设备波动影响的时钟同步电路，温度波动或电源的波动。

3. 发明授权

US5585754A Integrated digital circuit 失效
标题翻译：集成数字电路
公开(公告)号：US5585754A
公开(公告)日：1996-12-17
申请号：US222279
申请日：1994-04-04
申请人： Masakazu Yamashina , Masayuki Mizuno
发明人： Masakazu Yamashina , Masayuki Mizuno
IPC分类号： H03K3/0231 , H03K5/13 , H03L7/081 , H03L7/099 , H03L7/18
CPC分类号： H03L7/0805 , H03K3/0231 , H03K5/133 , H03L7/0812 , H03L7/0995 , H03L7/18
摘要： An integrated digital circuit includes an oscillation circuit comprising basic gate circuits having the number of stages proportional to the number of gates existing in the critical path of a synchronized circuit network and capable of controlling an oscillating frequency by at least one control signal line. A synchronized circuit network constructed with basic gate circuits capable of controlling the delay time by at least one control signal line operates synchronously by an oscillation signal transfer line. A control circuit controls the oscillation circuit and the synchronized circuit network using the control signal line so that the frequency of signal input from an externally input signal line is equalized with the frequency of signal from the oscillation circuit. Thus, the synchronized circuit network can be always operated at the frequency obtained from the oscillation signal transfer line even though the delay time of the basic gate circuit varied by variations of the device characteristics and the like.
摘要翻译：集成数字电路包括振荡电路，其包括具有与存在于同步电路网络的关键路径中的门数成比例的级数的基本门电路，并且能够通过至少一个控制信号线来控制振荡频率。由能够通过至少一个控制信号线控制延迟时间的基本门电路构成的同步电路网络由振荡信号传输线同步操作。控制电路使用控制信号线控制振荡电路和同步电路网络，使得从外部输入信号线输入的信号的频率与来自振荡电路的信号的频率相等。因此，即使基本门电路的延迟时间由设备特性等的变化而变化，同步电路网络也可以始终以从振荡信号传输线获得的频率进行工作。

4. 发明授权

US5801570A Semiconductor intergrated circuit with MOS transistors compensated of characteristic and performance deviations and deviation compensation system therein 失效
标题翻译：具有MOS晶体管的半导体集成电路补偿其特性和性能偏差以及偏差补偿系统
公开(公告)号：US5801570A
公开(公告)日：1998-09-01
申请号：US859089
申请日：1997-05-20
申请人： Masayuki Mizuno , Masakazu Yamashina
发明人： Masayuki Mizuno , Masakazu Yamashina
IPC分类号： H01L27/04 , G05F3/24 , G11C11/407 , H01L21/822 , H03K17/30 , H03K19/00 , H03K19/003 , H03L7/07 , H03L7/081 , H03L7/089 , G06G7/12
CPC分类号： H03L7/0805 , H03K19/0013 , H03K19/00384 , H03L7/07 , H03L7/0812 , G05F3/247 , H03L7/0891
摘要： A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.
摘要翻译：在其基板电极处彼此连接以具有衬底电位的多个MOS晶体管通过具有独立于衬底电位的电源电位的电源的组合进行偏差补偿，连接到源电极的电源线的每个MOS晶体管的采样电路，由采样的一个MOS晶体管构成的采样电路，检测电路，用于检测采样电路的动作，以提供表示检测到的采样电路的动作与参考动作之间的差异的检测信号以及连接在电源和电源线之间的电压发生器，电压发生器根据检测信号产生电压。

5. 发明授权

US5742195A Semiconductor integrated circuit with MOS Transistors compensated of characteristic and performance deviations and deviation compensation system therein 失效
标题翻译：具有MOS晶体管的半导体集成电路补偿了其中的特性和性能偏差和偏差补偿系统
公开(公告)号：US5742195A
公开(公告)日：1998-04-21
申请号：US597582
申请日：1996-02-02
申请人： Masayuki Mizuno , Masakazu Yamashina
发明人： Masayuki Mizuno , Masakazu Yamashina
IPC分类号： H01L27/04 , G05F3/24 , G11C11/407 , H01L21/822 , H03K17/30 , H03K19/00 , H03K19/003 , H03L7/07 , H03L7/081 , H03L7/089 , G06G7/12
CPC分类号： H03L7/0805 , H03K19/0013 , H03K19/00384 , H03L7/07 , H03L7/0812 , G05F3/247 , H03L7/0891
摘要： A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.
摘要翻译：在其基板电极处彼此连接以具有衬底电位的多个MOS晶体管通过具有独立于衬底电位的电源电位的电源的组合进行偏差补偿，连接到源电极的电源线的每个MOS晶体管的采样电路，由采样的一个MOS晶体管构成的采样电路，检测电路，用于检测采样电路的动作，以提供表示检测到的采样电路的动作与参考动作之间的差异的检测信号以及连接在电源和电源线之间的电压发生器，电压发生器根据检测信号产生电压。

6. 发明授权

US5559461A Drive circuit detecting slow signal transition 失效
标题翻译：驱动电路检测慢信号转换
公开(公告)号：US5559461A
公开(公告)日：1996-09-24
申请号：US495032
申请日：1995-06-27
申请人： Masakazu Yamashina , Youichi Koseki , Masayuki Mizuno
发明人： Masakazu Yamashina , Youichi Koseki , Masayuki Mizuno
IPC分类号： H03K19/0175 , H03K5/1534 , H03K17/16 , H03K5/22
CPC分类号： H03K5/1534
摘要： A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.
摘要翻译：驱动电路包括第一和第二电路部分。第一电路部分在输入信号的瞬态周期的初始阶段保持其在信号转换之前的输出电平，并且在瞬变周期之后提供响应于信号转换的输出信号。第二电路部分具有接收输入信号的第一电路部分和响应于输入信号的第二电路部分和第一电路部分的输出，以加速第一电路部分的信号转换。由于寄生电容和电阻大而导致的信号转换信号延迟可以由驱动电路恢复。驱动电路具有较大的噪声容限，并在高速和宽频率范围内工作。

7. 发明授权

US6094068A CMOS logic circuit and method of driving the same 失效
标题翻译： CMOS逻辑电路及其驱动方法
公开(公告)号：US6094068A
公开(公告)日：2000-07-25
申请号：US98307
申请日：1998-06-18
申请人： Masahiro Nomura , Masakazu Yamashina
发明人： Masahiro Nomura , Masakazu Yamashina
IPC分类号： H01L27/04 , H01L21/822 , H01L27/092 , H03K19/017 , H03K19/094 , H03K19/0948 , H03K19/0175 , H03K3/01 , H03K19/003
CPC分类号： H01L27/092 , H03K19/01707
摘要： A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.
摘要翻译：一种CMOS逻辑电路，包括（a）PMOS晶体管，（b）NMOS晶体管，（c）仅在PMOS晶体管的栅极和衬底之间电连接的第一耦合电容器，以及（d）电连接的第二耦合电容器在NMOS晶体管的栅极和漏极之间，其中PMOS和NMOS晶体管包括在传输到栅极的信号的上升沿期间使其高于相关参考电压的衬底电压，并且在下降沿期间低于相关参考电压信号。 PMOS和NMOS晶体管的栅极彼此电连接，PMOS和NMOS晶体管的漏极彼此电连接，并且输入信号被引入到电连接的栅极中，并且输出信号通过电连接下水道。

8. 发明授权

US07366821B2 High-speed memory system 有权
标题翻译：高速内存系统
公开(公告)号：US07366821B2
公开(公告)日：2008-04-29
申请号：US10311687
申请日：2001-06-20
申请人： Muneo Fukaishi , Masato Motomura , Yoshiharu Aimoto , Masakazu Yamashina
发明人： Muneo Fukaishi , Masato Motomura , Yoshiharu Aimoto , Masakazu Yamashina
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G11C7/1057 , G06F13/1684 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.
摘要翻译：存储器系统具有存储器控制器和多个存储器。多个存储器经由开关连接到连接到存储器控制器的总线的一端，其中多个存储器由开关控制。通过抑制总线上的反射和负载，可以获得更高的数据传输速度。

9. 发明授权

US4985861A High speed digital signal processor for signed digit numbers 失效
标题翻译：高速数字信号处理器，用于带符号位数
公开(公告)号：US4985861A
公开(公告)日：1991-01-15
申请号：US302346
申请日：1989-01-27
申请人： Masakazu Yamashina , Hachiro Yamada , Tadayoshi Enomoto
发明人： Masakazu Yamashina , Hachiro Yamada , Tadayoshi Enomoto
IPC分类号： G06F7/52 , G06F7/48 , G06F7/49 , G06F7/50 , G06F17/10
CPC分类号： G06F7/4824
摘要： For improvement in processing speed, a high-speed digital signal processor has a feedback loop from a register which stores the calculating result produced by a Signed Digit (SD) arithmetic unit to one of the input ports of the SD arithmetic unit. The SD arithmetic unit executes an arithmetic operation on an input digital signal and the arithmetic result is formed of both signed digit numbers without the need to convert the calculation result represented by an SD number into a binary number.

10. 发明授权

US4849921A Arithmetic circuit for calculating the absolute value of the difference between a pair of input signals 失效
标题翻译：用于计算一对输入信号之差的绝对值的算术电路
公开(公告)号：US4849921A
公开(公告)日：1989-07-18
申请号：US876026
申请日：1986-06-19
申请人： Masaaki Yasumoto , Tadayoshi Enomoto , Masakazu Yamashina
发明人： Masaaki Yasumoto , Tadayoshi Enomoto , Masakazu Yamashina
IPC分类号： G06F7/544
CPC分类号： G06F7/544 , G06F2207/5442
摘要： An arithmetic circuit has a first subtracter receiving first and second input signals which are composed of a plurality of bits and operative to output a first output signal representative of the first input signal minus the second input signal, and a second subtracter receiving the first and second input signals so as to output a second output signal representative of the second input signal minus the first input signal. A selector receives the first and second output signals and operates in response to one of the first and second output signals so as to alternately output the first and second output signals.
摘要翻译：算术电路具有接收第一和第二输入信号的第一减法器，该第一和第二输入信号由多个位组成，并且可操作以输出表示第一输入信号减去第二输入信号的第一输出信号;以及第二减法器，接收第一和第二以输出表示第二输入信号的第二输出信号减去第一输入信号。选择器接收第一和第二输出信号，并且响应于第一和第二输出信号之一而操作，以交替地输出第一和第二输出信号。

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