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    • 1. 发明授权
    • Drive circuit detecting slow signal transition
    • 驱动电路检测慢信号转换
    • US5559461A
    • 1996-09-24
    • US495032
    • 1995-06-27
    • Masakazu YamashinaYouichi KosekiMasayuki Mizuno
    • Masakazu YamashinaYouichi KosekiMasayuki Mizuno
    • H03K19/0175H03K5/1534H03K17/16H03K5/22
    • H03K5/1534
    • A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.
    • 驱动电路包括第一和第二电路部分。 第一电路部分在输入信号的瞬态周期的初始阶段保持其在信号转换之前的输出电平,并且在瞬变周期之后提供响应于信号转换的输出信号。 第二电路部分具有接收输入信号的第一电路部分和响应于输入信号的第二电路部分和第一电路部分的输出,以加速第一电路部分的信号转换。 由于寄生电容和电阻大而导致的信号转换信号延迟可以由驱动电路恢复。 驱动电路具有较大的噪声容限,并在高速和宽频率范围内工作。
    • 2. 发明授权
    • High speed synchronization circuit in semiconductor integrated circuit
    • 半导体集成电路中的高速同步电路
    • US06229360B1
    • 2001-05-08
    • US09149282
    • 1998-09-09
    • Masayuki MizunoMasakazu Yamashina
    • Masayuki MizunoMasakazu Yamashina
    • H03K504
    • H03K5/135G06F1/10H03K5/1252
    • A first latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of one direction of a clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, and a second latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of the other direction of the clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, are provided. A desired logic circuit is connected between the first and second latching circuits. By synchronously operating the first and second latching circuits by supplying a common clock signal, a clock synchronization circuit not influenced by fluctuation of the device, fluctuation of temperature or power source can be formed.
    • 第一锁存电路响应于输入到时钟端子的时钟信号的一个方向的电平转变定时将输入信号从输入端子传送到输出端子一段预定的周期,并且将输出端子的信号状态保持在 以及第二锁存电路,响应于输入到时钟端子的时钟信号的另一个方向的电平转换定时,将输入信号从输入端子输出到输出端子一段预定时间段,并且保持信号 提供了剩余时段的输出端子的状态。 期望的逻辑电路连接在第一和第二锁存电路之间。 通过提供公共时钟信号来同步操作第一和第二锁存电路,可以形成不受设备波动影响的时钟同步电路,温度波动或电源的波动。
    • 3. 发明授权
    • Driver circuitry adjusted to allow high speed driving and reduce
potential variations of interconnections
    • 驱动电路被调整以允许高速驱动并减少互连的潜在变化
    • US5686853A
    • 1997-11-11
    • US580485
    • 1995-12-29
    • Tomofumi IimaMasakazu YamashinaMasayuki Mizuno
    • Tomofumi IimaMasakazu YamashinaMasayuki Mizuno
    • H03K17/04H03K17/687H03K19/017H03K19/20
    • H03K19/01707
    • The present invention provides a driver circuitry having a single input terminal for receiving an input signal of binary digits consisting of high and low levels, and at least first and second output terminals, wherein the input signal is varied almost linearly in a first time period so as to be shifted between high and low levels, the driver circuitry comprises first and second control circuits. The first control circuit is coupled to the input terminal for receiving the input signal. The first control circuit is also coupled to the first output terminal for outputting a first output signal of binary digits via the first output terminal. The first control circuit is biased between a high voltage line which supplies a high level of voltage and a low voltage line which supplies a low level of voltage. The first control circuit is adjusted to shift the first output signal between the high and low levels within an initial period of the first time period and then keep the first output signal at the shifted one of the low and high levels until after the first time period expired. The second control circuit is coupled to the input terminal for receiving the input signal. The second control circuit is also coupled to the second output terminal for outputting a second output signal of binary digits via the second output terminal. The second control circuit is biased between the high voltage line and the low voltage line. The second control circuit is adjusted to keep the second output signal at one level of the low and high levels at least until the time approaches the termination of the first time period and then shift the second output signal from the one level to another level within a second time period which is short as the initial period of the first time period.
    • 本发明提供了一种驱动器电路,其具有用于接收由高电平和低电平组成的二进制数字的输入信号的单个输入端以及至少第一和第二输出端,其中输入信号在第一时间段内几乎线性地变化,因此 为了在高电平和低电平之间移动,驱动器电路包括第一和第二控制电路。 第一控制电路耦合到输入端以接收输入信号。 第一控制电路还耦合到第一输出端子,用于经由第一输出端子输出二进制数字的第一输出信号。 第一控制电路在提供高电平的高压线路和提供低电平的低电压线路之间被偏置。 调整第一控制电路以在第一时间周期的初始时段内将高电平和低电平之间的第一输出信号移位,然后将第一输出信号保持在低电平和高电平中的移位的一个,直到第一时间段 已过期 第二控制电路耦合到输入端以接收输入信号。 第二控制电路还耦合到第二输出端子,用于经由第二输出端子输出二进制数字的第二输出信号。 第二控制电路在高电压线路和低电压线路之间被偏置。 调整第二控制电路以将第二输出信号保持在低电平和高电平的一个电平,至少直到时间接近第一时间段的终止,然后将第二输出信号从一个电平移位到另一个电平内 作为第一时间段的初始期间的第二时间段。
    • 4. 发明授权
    • Integrated digital circuit
    • 集成数字电路
    • US5585754A
    • 1996-12-17
    • US222279
    • 1994-04-04
    • Masakazu YamashinaMasayuki Mizuno
    • Masakazu YamashinaMasayuki Mizuno
    • H03K3/0231H03K5/13H03L7/081H03L7/099H03L7/18
    • H03L7/0805H03K3/0231H03K5/133H03L7/0812H03L7/0995H03L7/18
    • An integrated digital circuit includes an oscillation circuit comprising basic gate circuits having the number of stages proportional to the number of gates existing in the critical path of a synchronized circuit network and capable of controlling an oscillating frequency by at least one control signal line. A synchronized circuit network constructed with basic gate circuits capable of controlling the delay time by at least one control signal line operates synchronously by an oscillation signal transfer line. A control circuit controls the oscillation circuit and the synchronized circuit network using the control signal line so that the frequency of signal input from an externally input signal line is equalized with the frequency of signal from the oscillation circuit. Thus, the synchronized circuit network can be always operated at the frequency obtained from the oscillation signal transfer line even though the delay time of the basic gate circuit varied by variations of the device characteristics and the like.
    • 集成数字电路包括振荡电路,其包括具有与存在于同步电路网络的关键路径中的门数成比例的级数的基本门电路,并且能够通过至少一个控制信号线来控制振荡频率。 由能够通过至少一个控制信号线控制延迟时间的基本门电路构成的同步电路网络由振荡信号传输线同步操作。 控制电路使用控制信号线控制振荡电路和同步电路网络,使得从外部输入信号线输入的信号的频率与来自振荡电路的信号的频率相等。 因此,即使基本门电路的延迟时间由设备特性等的变化而变化,同步电路网络也可以始终以从振荡信号传输线获得的频率进行工作。
    • 7. 发明授权
    • CMOS logic circuit and method of driving the same
    • CMOS逻辑电路及其驱动方法
    • US6094068A
    • 2000-07-25
    • US98307
    • 1998-06-18
    • Masahiro NomuraMasakazu Yamashina
    • Masahiro NomuraMasakazu Yamashina
    • H01L27/04H01L21/822H01L27/092H03K19/017H03K19/094H03K19/0948H03K19/0175H03K3/01H03K19/003
    • H01L27/092H03K19/01707
    • A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.
    • 一种CMOS逻辑电路,包括(a)PMOS晶体管,(b)NMOS晶体管,(c)仅在PMOS晶体管的栅极和衬底之间电连接的第一耦合电容器,以及(d)电连接的第二耦合电容器 在NMOS晶体管的栅极和漏极之间,其中PMOS和NMOS晶体管包括在传输到栅极的信号的上升沿期间使其高于相关参考电压的衬底电压,并且在下降沿期间低于相关参考电压 信号。 PMOS和NMOS晶体管的栅极彼此电连接,PMOS和NMOS晶体管的漏极彼此电连接,并且输入信号被引入到电连接的栅极中,并且输出信号通过电 连接下水道。