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1. 发明授权

US06675239B1 Method and apparatus for providing commands to a command memory 有权
标题翻译：用于向命令存储器提供命令的方法和装置
公开(公告)号：US06675239B1
公开(公告)日：2004-01-06
申请号：US09412145
申请日：1999-10-05
申请人： Timothy Van Hook , Robert Mace
发明人： Timothy Van Hook , Robert Mace
IPC分类号： G06F300
CPC分类号： G06F9/3879
摘要： The invention provides a method of providing commands to a command memory where a graphics processor will have commands available for execution as long as there are commands available. The command memory includes a first indicator to identify the command location most recently accessed by the graphics processor. A second indicator identifies the number of commands locations available to write commands based on the most recently accessed command location. As a result of the invention, the application processor only checks the availability of space to write commands after it has written enough commands to fill the command memory. On the graphics processor side, the command memory is never empty unless the graphics processor executes and consumes instructions faster than the instructions are written. It is also possible to associate a graphics mode with each address range. In this way, mode can be indicated without specifically sending mode information with each command.
摘要翻译：本发明提供了一种向命令存储器提供命令的方法，其中图形处理器将具有可用于执行的命令，只要存在命令即可。命令存储器包括用于识别由图形处理器最近访问的命令位置的第一指示符。第二个指示符基于最近访问的命令位置来识别可用于写入命令的命令位置的数量。作为本发明的结果，应用处理器在写入足够的命令以填充命令存储器之后，仅检查写入命令的空间的可用性。在图形处理器端，命令存储器从不为空，除非图形处理器执行并且比写入指令更快地消耗指令。还可以将图形模式与每个地址范围相关联。以这种方式，可以指示模式，而不用每个命令专门发送模式信息。

2. 发明申请

US20070070083A1 Graphics system with copy out conversions between embedded frame buffer and main memory 有权
公开(公告)号：US20070070083A1
公开(公告)日：2007-03-29
申请号：US11604374
申请日：2006-11-27
申请人： Farhad Fouladi , Mark Leather , Robert Moore , Howard Cheng , Timothy Van Hook
发明人： Farhad Fouladi , Mark Leather , Robert Moore , Howard Cheng , Timothy Van Hook
IPC分类号： G09G5/02
CPC分类号： G09G5/363 , G06T15/005 , G09G5/02 , G09G5/391 , G09G5/393 , G09G5/399 , G09G2320/0247 , G09G2320/0276 , G09G2340/0407 , G09G2360/127
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. The formatted data is either transferred to a display buffer, for use by the video interface, or to a texture buffer, for use as a texture by the graphics pipeline in a subsequent rendering process.

3. 发明授权

US06549210B1 Method and apparatus for cache index hashing 有权
标题翻译：缓存索引散列的方法和装置
公开(公告)号：US06549210B1
公开(公告)日：2003-04-15
申请号：US09244449
申请日：1999-02-03
申请人： Timothy Van Hook , Anthony P. DeLaurier
发明人： Timothy Van Hook , Anthony P. DeLaurier
IPC分类号： G09G537
CPC分类号： G06T15/04 , G06F12/0864 , G06F12/0875 , G06T1/60 , G06T2200/28
摘要： The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.
摘要翻译：本发明提供了一种产生缓存索引的方法，该方法降低了相邻地址映射到相同高速缓存区域的可能性。优化散列过程以对输入数据中的小变化敏感，使得类似的输入数据组优选不会产生相同或甚至相似的输出数据。在渲染图形图像时执行的排序的存储器访问可能涉及对相对相似的存储器位置的多次访问。因此，确定在存储器位置的信息的哪个位置将被存储的索引值的散列，同时该信息在高速缓存中降低类似存储器的可能性位置存储在相同的缓存位置。因此，提高了缓存效率和性能。

4. 发明授权

US06490652B1 Method and apparatus for decoupled retrieval of cache miss data 有权
标题翻译：用于缓存未命中数据解耦检索的方法和装置
公开(公告)号：US06490652B1
公开(公告)日：2002-12-03
申请号：US09244692
申请日：1999-02-03
申请人： Timothy Van Hook , Anthony P. DeLaurier
发明人： Timothy Van Hook , Anthony P. DeLaurier
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0855 , G06F12/0875
摘要： The invention provides a method of operating a cache memory so that operation is optimized. Instead of fetching data immediately upon a cache miss, the present invention continues with subsequent cache accesses. Decoupled from cache access, cache misses are fetched to cache. During operation, for each request in a sequence of data requests, it is determined if the requested data can be found in cache memory. If the data is not found in the cache, the next request in the sequence is processed without first retrieving the data pending from the earlier request. A miss list is generated for each of the requests in the sequence of requests whose data is not found in the cache. The data that is associated with the requests in the miss list is obtained from DRAM and used to satisfy the requests. Some cache lines may have one or more pending hits to data associated with the cache line. Those requests are kept in a pending hits list and processed in order as required. There may also be pending misses kept in a pending misses list where the list contains one or more pending misses to data associated with the cache line. A flag or indicator is set for a cache line when there are misses associated with the cache line.
摘要翻译：本发明提供了一种操作高速缓冲存储器的方法，使得操作被优化。代替在高速缓存未命中立即获取数据，本发明继续随后的高速缓存访问。从缓存访问中解耦，缓存未命中被提取到缓存。在操作期间，对于数据请求序列中的每个请求，确定是否可以在高速缓冲存储器中找到所请求的数据。如果在高速缓存中没有找到数据，则处理该序列中的下一个请求，而不首先从较早的请求中检索待处理的数据。为缓存中未找到数据的请求序列中的每个请求生成一个未命中列表。与未命中列表中的请求相关联的数据从DRAM获得并用于满足请求。某些高速缓存行可能具有与高速缓存行相关联的数据的一个或多个待处理命中。这些请求保存在待处理的匹配列表中，并根据需要按顺序进行处理。在挂起的未命中列表中还可能存在未决的未命中，其中列表包含与高速缓存行相关联的数据的一个或多个未决命中。当与高速缓存行相关联的未命中时，为高速缓存行设置标志或指示符。

5. 发明授权

US07944441B2 Compression and decompression of data using plane equations 有权
标题翻译：使用平面方程压缩和解压缩数据
公开(公告)号：US07944441B2
公开(公告)日：2011-05-17
申请号：US11764858
申请日：2007-06-19
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G06T15/00
CPC分类号： G06T9/00
摘要： The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.
摘要翻译：本发明提供了一种用于压缩和解压缩图像数据的深度或Z分量的方案。图像数据被分组成多个瓦片。执行测试以确定是否可以压缩瓦片，使其压缩后的大小小于压缩前的大小。如果是这样，瓦片被压缩。瓦片表包括可以为压缩的每个瓦片设置的标志。在一个方案中，每个瓦片包括4×4个像素块。对于每个像素，确定可见深度复杂度，其中深度复杂度的每个可见水平由平面方程表示。根据深度复杂度，选择在高速缓存行中存储多个平面方程式的压缩方案。压缩方案可以与非抽样或多采样数据一起使用，并在多采样环境中提供更高级别的压缩。

6. 发明申请

US20090249039A1 Providing Extended Precision in SIMD Vector Arithmetic Operations 有权
标题翻译：在SIMD矢量算术运算中提供扩展精度
公开(公告)号：US20090249039A1
公开(公告)日：2009-10-01
申请号：US12480414
申请日：2009-06-08
申请人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

7. 发明授权

US07995069B2 Graphics system with embedded frame buffer having reconfigurable pixel formats 有权
标题翻译：具有嵌入式帧缓冲器的图形系统具有可重构像素格式
公开(公告)号：US07995069B2
公开(公告)日：2011-08-09
申请号：US12461238
申请日：2009-08-05
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G09G5/397 , G09G5/36 , G09G5/02
CPC分类号： G06T15/005 , G09G5/363
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.
摘要翻译：包括定制图形和音频处理器的图形系统产生令人兴奋的2D和3D图形和环绕声。该系统包括包括3D图形流水线和音频数字信号处理器的图形和音频处理器。图形系统具有图形处理器，其包括用于在将帧数据发送到诸如主存储器的外部位置之前存储帧数据的嵌入式帧缓冲器。嵌入式帧缓冲器可选择配置为存储以下像素格式：点采样RGB颜色和深度，超采样RGB颜色和深度以及YUV（亮度/色度）。提供了图形命令，使得编程器能够逐帧地为任何像素格式配置嵌入式帧缓冲器。

8. 发明申请

US20080150935A1 COMPRESSION AND DECOMPRESSION OF DATA USING PLANE EQUATIONS 有权
标题翻译：使用平面方程的数据的压缩和分解
公开(公告)号：US20080150935A1
公开(公告)日：2008-06-26
申请号：US11764858
申请日：2007-06-19
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G06T1/00 , G06K9/36
CPC分类号： G06T9/00
摘要： The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.
摘要翻译：本发明提供了一种用于压缩和解压缩图像数据的深度或Z分量的方案。图像数据被分组成多个瓦片。执行测试以确定是否可以压缩瓦片，使其压缩后的大小小于压缩前的大小。如果是这样，瓦片被压缩。瓦片表包括可以为压缩的每个瓦片设置的标志。在一个方案中，每个瓦片包括4×4像素块。对于每个像素，确定可见深度复杂度，其中深度复杂度的每个可见水平由平面方程表示。根据深度复杂度，选择在高速缓存行中存储多个平面方程式的压缩方案。压缩方案可以与非抽样或多采样数据一起使用，并在多采样环境中提供更高级别的压缩。

9. 发明授权

US07242400B2 Compression and decompression of data using plane equations 有权
标题翻译：使用平面方程压缩和解压缩数据
公开(公告)号：US07242400B2
公开(公告)日：2007-07-10
申请号：US10293003
申请日：2002-11-13
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G06T1/00
CPC分类号： G06T9/00
摘要： The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.
摘要翻译：本发明提供了一种用于压缩和解压缩图像数据的深度或Z分量的方案。图像数据被分组成多个瓦片。执行测试以确定是否可以压缩瓦片，使其压缩后的大小小于压缩前的大小。如果是这样，瓦片被压缩。瓦片表包括可以为压缩的每个瓦片设置的标志。在一个方案中，每个瓦片包括4×4像素块。对于每个像素，确定可见深度复杂度，其中深度复杂度的每个可见水平由平面方程表示。根据深度复杂度，选择在高速缓存行中存储多个平面方程式的压缩方案。压缩方案可以与非抽样或多采样数据一起使用，并在多采样环境中提供更高级别的压缩。

10. 发明申请

US20070250683A1 Alignment and ordering of vector elements for single instruction multiple data processing 有权
公开(公告)号：US20070250683A1
公开(公告)日：2007-10-25
申请号：US11702659
申请日：2007-02-06
申请人： Timothy Van Hook , Peter Hsu , William Huffman , Henry Moreton , Earl Killian
发明人： Timothy Van Hook , Peter Hsu , William Huffman , Henry Moreton , Earl Killian
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30167 , G06F9/3885 , G06F9/3887
摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

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