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1. 发明授权

US06549210B1 Method and apparatus for cache index hashing 有权
标题翻译：缓存索引散列的方法和装置
公开(公告)号：US06549210B1
公开(公告)日：2003-04-15
申请号：US09244449
申请日：1999-02-03
申请人： Timothy Van Hook , Anthony P. DeLaurier
发明人： Timothy Van Hook , Anthony P. DeLaurier
IPC分类号： G09G537
CPC分类号： G06T15/04 , G06F12/0864 , G06F12/0875 , G06T1/60 , G06T2200/28
摘要： The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.
摘要翻译：本发明提供了一种产生缓存索引的方法，该方法降低了相邻地址映射到相同高速缓存区域的可能性。优化散列过程以对输入数据中的小变化敏感，使得类似的输入数据组优选不会产生相同或甚至相似的输出数据。在渲染图形图像时执行的排序的存储器访问可能涉及对相对相似的存储器位置的多次访问。因此，确定在存储器位置的信息的哪个位置将被存储的索引值的散列，同时该信息在高速缓存中降低类似存储器的可能性位置存储在相同的缓存位置。因此，提高了缓存效率和性能。

2. 发明授权

US06490652B1 Method and apparatus for decoupled retrieval of cache miss data 有权
标题翻译：用于缓存未命中数据解耦检索的方法和装置
公开(公告)号：US06490652B1
公开(公告)日：2002-12-03
申请号：US09244692
申请日：1999-02-03
申请人： Timothy Van Hook , Anthony P. DeLaurier
发明人： Timothy Van Hook , Anthony P. DeLaurier
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0855 , G06F12/0875
摘要： The invention provides a method of operating a cache memory so that operation is optimized. Instead of fetching data immediately upon a cache miss, the present invention continues with subsequent cache accesses. Decoupled from cache access, cache misses are fetched to cache. During operation, for each request in a sequence of data requests, it is determined if the requested data can be found in cache memory. If the data is not found in the cache, the next request in the sequence is processed without first retrieving the data pending from the earlier request. A miss list is generated for each of the requests in the sequence of requests whose data is not found in the cache. The data that is associated with the requests in the miss list is obtained from DRAM and used to satisfy the requests. Some cache lines may have one or more pending hits to data associated with the cache line. Those requests are kept in a pending hits list and processed in order as required. There may also be pending misses kept in a pending misses list where the list contains one or more pending misses to data associated with the cache line. A flag or indicator is set for a cache line when there are misses associated with the cache line.
摘要翻译：本发明提供了一种操作高速缓冲存储器的方法，使得操作被优化。代替在高速缓存未命中立即获取数据，本发明继续随后的高速缓存访问。从缓存访问中解耦，缓存未命中被提取到缓存。在操作期间，对于数据请求序列中的每个请求，确定是否可以在高速缓冲存储器中找到所请求的数据。如果在高速缓存中没有找到数据，则处理该序列中的下一个请求，而不首先从较早的请求中检索待处理的数据。为缓存中未找到数据的请求序列中的每个请求生成一个未命中列表。与未命中列表中的请求相关联的数据从DRAM获得并用于满足请求。某些高速缓存行可能具有与高速缓存行相关联的数据的一个或多个待处理命中。这些请求保存在待处理的匹配列表中，并根据需要按顺序进行处理。在挂起的未命中列表中还可能存在未决的未命中，其中列表包含与高速缓存行相关联的数据的一个或多个未决命中。当与高速缓存行相关联的未命中时，为高速缓存行设置标志或指示符。

3. 发明申请

US20070250683A1 Alignment and ordering of vector elements for single instruction multiple data processing 有权
公开(公告)号：US20070250683A1
公开(公告)日：2007-10-25
申请号：US11702659
申请日：2007-02-06
申请人： Timothy Van Hook , Peter Hsu , William Huffman , Henry Moreton , Earl Killian
发明人： Timothy Van Hook , Peter Hsu , William Huffman , Henry Moreton , Earl Killian
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30167 , G06F9/3885 , G06F9/3887
摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

4. 发明授权

US07159100B2 Method for providing extended precision in SIMD vector arithmetic operations 有权
标题翻译：在SIMD向量算术运算中提供扩展精度的方法
公开(公告)号：US07159100B2
公开(公告)日：2007-01-02
申请号：US09223046
申请日：1998-12-30
申请人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一向量寄存器和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。然后，本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行结果写入累加器。然后，累加器中的每个元素被变换成N位元素并存储到存储器中。

5. 发明申请

US20060197768A1 Graphics system with embedded frame buffer having reconfigurable pixel formats 有权
标题翻译：具有嵌入式帧缓冲器的图形系统具有可重构像素格式
公开(公告)号：US20060197768A1
公开(公告)日：2006-09-07
申请号：US11398531
申请日：2006-04-06
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G09G5/397
CPC分类号： G06T15/005 , G09G5/363
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.
摘要翻译：包括定制图形和音频处理器的图形系统产生令人兴奋的2D和3D图形和环绕声。该系统包括包括3D图形流水线和音频数字信号处理器的图形和音频处理器。图形系统具有图形处理器，其包括用于在将帧数据发送到诸如主存储器的外部位置之前存储帧数据的嵌入式帧缓冲器。嵌入式帧缓冲器可选择配置为存储以下像素格式：点采样RGB颜色和深度，超采样RGB颜色和深度以及YUV（亮度/色度）。提供了图形命令，使得编程器能够逐帧地为任何像素格式配置嵌入式帧缓冲器。

6. 发明申请

US20050237337A1 Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system 有权
公开(公告)号：US20050237337A1
公开(公告)日：2005-10-27
申请号：US11152283
申请日：2005-06-15
申请人： Mark Leather , Robert Drebin , Timothy Van Hook
发明人： Mark Leather , Robert Drebin , Timothy Van Hook
IPC分类号： G06T15/00 , G06T15/04 , G09G5/00 , G06T11/40
CPC分类号： G06T15/04 , G06T15/005
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate/data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate/data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate/data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle/stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle/stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.

7. 发明申请

US20050162436A1 Graphics system with embedded frame buffer having reconfigurable pixel formats 有权
公开(公告)号：US20050162436A1
公开(公告)日：2005-07-28
申请号：US11082854
申请日：2005-03-18
申请人： Timothy Van Hook , Farhad Fouladi
发明人： Timothy Van Hook , Farhad Fouladi
IPC分类号： G06T15/00 , G09G5/397 , G09G5/02
CPC分类号： G06T15/005 , A63F2300/203
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.

8. 发明申请

US20050125630A1 Method and apparatus for obtaining a scalar value directly from a vector register 有权
公开(公告)号：US20050125630A1
公开(公告)日：2005-06-09
申请号：US11032055
申请日：2005-01-11
申请人： Yu-Chung Liao , Peter Sandon , Howard Cheng , Timothy Van Hook
发明人： Yu-Chung Liao , Peter Sandon , Howard Cheng , Timothy Van Hook
IPC分类号： G06F7/00 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/318 , G06F17/16 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30185 , G06F9/30192
摘要： A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.

9. 发明授权

US06675239B1 Method and apparatus for providing commands to a command memory 有权
标题翻译：用于向命令存储器提供命令的方法和装置
公开(公告)号：US06675239B1
公开(公告)日：2004-01-06
申请号：US09412145
申请日：1999-10-05
申请人： Timothy Van Hook , Robert Mace
发明人： Timothy Van Hook , Robert Mace
IPC分类号： G06F300
CPC分类号： G06F9/3879
摘要： The invention provides a method of providing commands to a command memory where a graphics processor will have commands available for execution as long as there are commands available. The command memory includes a first indicator to identify the command location most recently accessed by the graphics processor. A second indicator identifies the number of commands locations available to write commands based on the most recently accessed command location. As a result of the invention, the application processor only checks the availability of space to write commands after it has written enough commands to fill the command memory. On the graphics processor side, the command memory is never empty unless the graphics processor executes and consumes instructions faster than the instructions are written. It is also possible to associate a graphics mode with each address range. In this way, mode can be indicated without specifically sending mode information with each command.
摘要翻译：本发明提供了一种向命令存储器提供命令的方法，其中图形处理器将具有可用于执行的命令，只要存在命令即可。命令存储器包括用于识别由图形处理器最近访问的命令位置的第一指示符。第二个指示符基于最近访问的命令位置来识别可用于写入命令的命令位置的数量。作为本发明的结果，应用处理器在写入足够的命令以填充命令存储器之后，仅检查写入命令的空间的可用性。在图形处理器端，命令存储器从不为空，除非图形处理器执行并且比写入指令更快地消耗指令。还可以将图形模式与每个地址范围相关联。以这种方式，可以指示模式，而不用每个命令专门发送模式信息。

10. 发明授权

US06353438B1 Cache organization—direct mapped cache 有权
标题翻译：缓存组织直接映射缓存
公开(公告)号：US06353438B1
公开(公告)日：2002-03-05
申请号：US09244690
申请日：1999-02-03
申请人： Timothy Van Hook , Anthony P. DeLaurier
发明人： Timothy Van Hook , Anthony P. DeLaurier
IPC分类号： G06T1140
CPC分类号： G06T1/60 , G06F12/0864
摘要： The invention provides for cache organization of texture information and a method and apparatus for accessing cached texture information and an index for cached information. Texels are represented in two dimensions and stored in groups referred to as tiles. Cache is configured to contain multiple tiles of texture image data, each tile being stored as a line in the cache. A cache line can be multidimensional (e.g., two or three or more dimensions) and may be viewed as an identifiable storage element in the cache. Memory may consist of a plurality of cache lines. Direct mapped cache may be utilized wherein each DRAM location maps to a single cache line. A tag table contains the tag information for all tiles currently stored in cache. A portion of the texel information may be utilized as an index assigned to a specific cache line. Another portion of the tag information identifies the tile currently stored in cache. A portion of the S bits and a portion of the T bits are utilized as the index and tile information. The tags may be organized into sections (referred to as tag banks) with the cache lines interleaved in two dimensions across the tag banks. Additionally, when mipmapping, the level of detail may be specified as part of the tag information. Cache access requests that are not currently active may also be stored in an interleaved list or queue until they are completed.
摘要翻译：本发明提供纹理信息的缓存组织以及用于访问缓存纹理信息的方法和装置以及用于缓存信息的索引。 Texels以二维表示，并以被称为瓦片的组存储。缓存被配置为包含纹理图像数据的多个瓦片，每个瓦片作为行存储在高速缓存中。高速缓存行可以是多维的（例如，两个或三个或更多个维度），并且可以被视为高速缓存中的可识别存储元件。存储器可以由多条缓存行组成。可以使用直接映射高速缓存，其中每个DRAM位置映射到单个高速缓存行。标签表包含当前存储在缓存中的所有图块的标签信息。纹理信息的一部分可以用作分配给特定高速缓存行的索引。标签信息的另一部分标识当前存储在高速缓存中的瓦片。 S比特的一部分和T比特的一部分被用作索引和瓦片信息。标签可以被组织成部分（称为标签库），其中高速缓存行在两个标签组之间交错。另外，当mipmap时，可以将细节级别指定为标签信息的一部分。当前没有活动的缓存访问请求也可以存储在交错列表或队列中，直到完成。

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