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    • 1. 发明授权
    • Method and apparatus for reducing transient noise in integrated circuits
    • 降低集成电路瞬态噪声的方法和装置
    • US4947063A
    • 1990-08-07
    • US161469
    • 1988-02-26
    • Timothy G. O'ShaughnessyDavid K. ChungRichard W. HullKenneth W. OuyangVictor G. PierottiJoseph A. Souza
    • Timothy G. O'ShaughnessyDavid K. ChungRichard W. HullKenneth W. OuyangVictor G. PierottiJoseph A. Souza
    • H03K17/16H03K19/003
    • H03K17/166H03K17/163H03K19/00361
    • The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise. A dynamic clamp suppresses voltage spikes extending outside the voltage supply operating range. A bias circuit arrangement compensates for sheet resistivity of the integrated circuit chip. If the resistance value of the sheet drops below a prescribed value, the fixed current is limited so it cannot exceed its designed value.
    • 在集成电路芯片的输出驱动器处产生的瞬态噪声通过在容性负载的二进制状态之间的整个转换间隔期间保持通过每个输出驱动器的斜坡形状电流而减小。 由固定电流源馈送的电容器连接在每个输出驱动级的输入端。 固定电流源和电容器被选择为在每个输出驱动级的输入端产生线性斜坡形控制电压,其以所述方式调节通过输出驱动级和封装电感的充电/放电电流。 专门设计的偏置电路降低了所产生的瞬态噪声对工艺变化和工作条件的敏感性。 从封装电感到用于固定电流源的偏置控制电路的反馈连接将与固定电流反向地调整固定电流与瞬态噪声。 动态钳位电压可以抑制电压工作范围以外的电压尖峰。 偏置电路布置补偿集成电路芯片的薄层电阻率。 如果纸张的电阻值低于规定值,则固定电流受到限制,因此不能超过设计值。
    • 2. 发明授权
    • CMOS integrated circuit having precision resistor elements
    • CMOS集成电路具有精密电阻元件
    • US4868482A
    • 1989-09-19
    • US104398
    • 1987-10-05
    • Timothy G. O'ShaughnessyMichael R. SpaurKenneth W. Ouyang
    • Timothy G. O'ShaughnessyMichael R. SpaurKenneth W. Ouyang
    • H03F3/345H03H11/46
    • H03F3/345H03H11/46
    • A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.
    • 提供一种电路,用于通过感测参考电阻器在集成电路上实现多个精密电阻器元件。 该电路包含第一电流源,该第一电流源使第一电流通过位于集成电路的导通或关闭的参考电阻以产生参考电压。 参考电压施加到精密高增益运算放大器的反相输入端。 第二电流源连接到在其欧姆区工作的第一MOS晶体管的漏极。 第二电流源也连接到高增益运算放大器的非反相输入。 运算放大器的输出电连接到第一和第二MOS晶体管的栅极。 在操作中,跨第二MOS晶体管产生精密电阻,其等于或定位在芯片上或芯片上的参考精密电阻器的电阻的一些可确定的倍数。 还公开了适用于该电路的运算放大器。
    • 6. 发明授权
    • Digital-to-analog converter with bit weight segmented arrays
    • 具有位权重分段阵列的数模转换器
    • US5017919A
    • 1991-05-21
    • US533885
    • 1990-06-06
    • Richard W. HullTimothy G. O'Shaughnessy
    • Richard W. HullTimothy G. O'Shaughnessy
    • H03M1/68H03M1/74
    • H03M1/682H03M1/747
    • A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal. The DAC further includes circuitry for producing a second bias voltage, a second set of current sources each biased by the second bias voltage to produce a switchable current having a multi-unit magnitude, and switching circuitry controlled by the decoded higher-order portion to cause a selected number of the multi-unit-magnitude currents to contribute to the analog-current signal.
    • CMOS集成电路中实现的DAC将多位数字信号转换为模拟电流信号。 数字信号的高阶部分(例如,一个字节的最高有效5位)与低阶部分(例如3个最低有效位)分开解码。 DAC包括用于产生第一偏置电压的电路,第一组电流源,每个电流源由第一偏置电压偏置以产生具有单位幅度的可切换电流,以及由解码的低阶部分控制的开关电路以引起所选择的数量 的单位幅度电流有助于模拟电流信号。 DAC还包括用于产生第二偏置电压的电路,每个由第二偏置电压偏置以产生具有多单位幅度的可切换电流的第二组电流源,以及由解码的高阶部分控制的开关电路, 选择数量的多单位幅度电流以有助于模拟电流信号。
    • 8. 发明授权
    • Schmitt trigger adapted to interface between different transistor
architectures
    • 施密特触发器适用于不同晶体管结构之间的接口
    • US4904884A
    • 1990-02-27
    • US184243
    • 1988-04-21
    • Timothy G. O'ShaughnessyDavid K. Chung
    • Timothy G. O'ShaughnessyDavid K. Chung
    • H03K3/3565
    • H03K3/3565
    • A Schmitt trigger having first and second complementary switches is biased to exhibit hysteresis, switching at a high threshold level when the input signal increases, and switching at a low threshold level when the input decreases. The source driver for the Schmitt trigger is coupled to the input of at least one of the complementary switches by transition circuitry, such that the signal level representing one binary value is shifted closer to the level of the power supply voltage corresponding to such binary value without changing the logical value of the signal from the source driver. In one embodiment, the first inverter is a MOS transistor, the threshold level of which is set by a bias voltage applied to the gate of another MOS transistor. The second inverter is a pair of complementary CMOS transistors. In another embodiment, the first inverter also comprises a pair of complementary CMOS transistors. The threshold level is set by selecting the W/L ratio of the CMOS transistors of the first inverter. In another embodiment the first inverter comprises a differential amplifier.
    • 具有第一和第二互补开关的施密特触发器被偏置以呈现迟滞,当输入信号增加时以高阈值电平切换,并且当输入减小时切换为低阈值电平。 施密特触发器的源极驱动器通过转换电路耦合至至少一个互补开关的输入,使得表示一个二进制值的信号电平更接近于对应于这样的二进制值的电源电压的电平,而没有 改变来自源驱动器的信号的逻辑值。 在一个实施例中,第一反相器是MOS晶体管,其阈值电平由施加到另一个MOS晶体管的栅极的偏置电压来设置。 第二个反相器是一对互补CMOS晶体管。 在另一实施例中,第一反相器还包括一对互补CMOS晶体管。 通过选择第一反相器的CMOS晶体管的W / L比来设置阈值电平。 在另一个实施例中,第一反相器包括差分放大器。