专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07080188B2 Method and system for embedded disk controllers 有权
标题翻译：嵌入式磁盘控制器的方法和系统
公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
IPC分类号： G06F13/36 , G06F13/24
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译：提供了一种嵌入式磁盘控制器的系统。该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

2. 发明授权

US06590733B1 Digital processing of pilot-tone amplitudes 有权
标题翻译：导频音幅度的数字处理
公开(公告)号：US06590733B1
公开(公告)日：2003-07-08
申请号：US09474175
申请日：1999-12-29
申请人： Rosser S. Wilson , Michael R. Spaur
发明人： Rosser S. Wilson , Michael R. Spaur
IPC分类号： G11B5596
CPC分类号： G11B5/5921
摘要： In a system having an input signal set with at least two signals having mutually exclusive frequencies f1 and f2 being part of the input signal set, whose amplitude is represented in an input digital representation, the amplitudes of each of the at least two signals are digitally represented. A digital representation of the frequency of each of the signals is derived. A digital representation of the sine function and of the cosine function of the frequency of each of the signals is derived based on the digital representation of the frequency. The digital representations of each of the sine and cosine functions is mixed with the input digital representation to derive digital representations of the sine and cosine functions of each of the signals. The digital representations of the sine and cosine functions of each of the signals are processed to derive a digital representation of the amplitude of each of the signals.
摘要翻译：在具有输入信号的系统中，具有至少两个具有相互排斥的频率的信号的信号，f1和f2是输入信号组的一部分，其幅度以输入数字表示形式表示，所述至少两个信号中的每一个的幅度是数字的代表。导出每个信号的频率的数字表示。基于频率的数字表示，导出每个信号的频率的正弦函数和余弦函数的数字表示。每个正弦和余弦函数的数字表示与输入数字表示混合，以导出每个信号的正弦和余弦函数的数字表示。每个信号的正弦和余弦函数的数字表示被处理以导出每个信号的振幅的数字表示。

3. 发明授权

US08189285B1 Method and system for automatic time base adjustment for disk drive servo controllers 有权
标题翻译：磁盘驱动器伺服控制器自动时基调整方法及系统
公开(公告)号：US08189285B1
公开(公告)日：2012-05-29
申请号：US12361121
申请日：2009-01-28
申请人： Michael R. Spaur , Raymond A. Sandoval
发明人： Michael R. Spaur , Raymond A. Sandoval
IPC分类号： G11B20/20
CPC分类号： G11B5/59616
摘要： A servo controller includes a first device that determines an adjusted servo-to-servo skew value. A servo field timer increments a timer value between consecutive servo fields, receives the adjusted servo-to-servo skew value, and adjusts an incremented timer value between the consecutive servo fields based on the adjusted servo-to-servo skew value.
摘要翻译：伺服控制器包括确定调整后的伺服至伺服偏移值的第一装置。伺服场定时器在连续伺服场之间递增定时器值，接收经调整的伺服至伺服偏移值，并根据调整后的伺服至伺服偏移值调整连续伺服场之间的增量定时器值。

4. 发明授权

US06529973B1 Programmable generic read channel control device 有权
标题翻译：可编程通用读通道控制器
公开(公告)号：US06529973B1
公开(公告)日：2003-03-04
申请号：US09576705
申请日：2000-05-22
申请人： Michael R. Spaur
发明人： Michael R. Spaur
IPC分类号： G06F100
CPC分类号： G06F3/0626 , G06F3/0655 , G06F3/0676
摘要： The present invention provides a programmable generic read channel control device and circuitry for generating an output signal to control read/write operations. The programmable generic read channel control device includes a set of extension timer, a set of configuration registers, a set of AND gates, and an OR gate. The extension timers are programmed to generate a set of pulses of programmable width in response to a read gate and write gate signal. Each of the pulses is defined by a leading edge pulse and a trailing edge pulse. The set of extension timers includes a short write gate extension timer configured to generate a write gate short leading edge pulse and a write gate short trailing edge pulse defining a write gate short pulse width. The configuration registers store a set of configuration data for the pulses with each configuration register storing one configuration data for either a leading edge or a trailing edge pulse of one of the pulses. The configuration data indicates whether the associated pulse is enabled. The AND gates are arranged to receive the pulses of programmable width with each AND gate receiving either a leading edge or a trailing edge of one of the pulses as a first input. Each AND gate also receiving a configuration data as a second input that allows the first input to be transmitted as an output signal when the configuration data at the second input is enabled. The OR gate is arranged to combine the output signals from the set of AND gates to generate the output signal such that the output signal is generated from only the leading or trailing edges of the pulses from the AND gates receiving the enable signals.
摘要翻译：本发明提供了一种可编程通用读通道控制装置和用于产生输出信号以控制读/写操作的电路。可编程通用读通道控制装置包括一组扩展定时器，一组配置寄存器，一组与门和一个或门。扩展定时器被编程为响应于读门限和写门信号产生一组可编程宽度的脉冲。每个脉冲由前沿脉冲和后沿脉冲定义。扩展定时器组包括短写入门扩展定时器，其被配置为产生写入门短前沿脉冲和限定写入门短脉冲宽度的写入门短后沿脉冲。配置寄存器存储一组脉冲配置数据，每个配置寄存器存储一个脉冲的前沿或后沿脉冲的一个配置数据。配置数据指示相关脉冲是否启用。 AND门布置为接收可编程宽度的脉冲，每个AND门接收作为第一输入的脉冲之一的前沿或后沿。当第二输入的配置数据被使能时，每个与门也接收作为第二输入的配置数据，该第二输入允许第一输入作为输出信号发送。 OR门被布置为组合来自该组与门的输出信号以产生输出信号，使得仅从接收使能信号的与门的脉冲的前沿或后沿产生输出信号。

5. 发明授权

US08116026B2 Method and system for head position control in embedded disk drive controllers 有权
标题翻译：嵌入式磁盘驱动器控制器中磁头位置控制的方法和系统
公开(公告)号：US08116026B2
公开(公告)日：2012-02-14
申请号：US12338071
申请日：2008-12-18
申请人： Michael R. Spaur , Raymond A. Sandoval
发明人： Michael R. Spaur , Raymond A. Sandoval
IPC分类号： G11B5/596
CPC分类号： G11B5/59655 , G11B5/59605
摘要： A track follow controller includes a burst selector selecting at least one burst pair based on burst pair selection data. A linear position calculator calculates a primary head position and a secondary head position based on the at least one burst pair, and calculates a head linear position based on the primary head position and the secondary head position.
摘要翻译：轨道跟随控制器包括基于突发组选择数据选择至少一个脉冲串对的突发选择器。线性位置计算器基于至少一个突发对来计算主要头部位置和次要头部位置，并且基于主要头部位置和次要头部位置来计算头部线性位置。

6. 发明授权

US07827387B1 Communication bus with hidden pre-fetch registers 有权
标题翻译：通信总线带有隐藏的预取寄存器
公开(公告)号：US07827387B1
公开(公告)日：2010-11-02
申请号：US11517927
申请日：2006-09-08
申请人： Kevin Kwan , Michael R. Spaur
发明人： Kevin Kwan , Michael R. Spaur
IPC分类号： G06F9/00
CPC分类号： G06F3/0608 , G06F3/0658 , G06F3/0676
摘要： A system-on-chip (SOC) includes a processor, a controller module for a hard disk drive, and a communication bus that provides a communication link between the processor and the controller module. The communication bus includes a multiplexer that includes an output and an input that receives data from a selected one of N registers associated with the controller module and propagates the data to the output, M address registers that store addresses of up to M ones of the N registers, M data registers that receive pre-fetch data that corresponds to the data from the output from the M ones of the N registers, and a second multiplexer that includes a second output and that reads the pre-fetch data from the M data registers and propagates the pre-fetch data to the second output. M and N are positive integers greater than two and N is greater than M.
摘要翻译：片上系统（SOC）包括处理器，用于硬盘驱动器的控制器模块以及提供处理器和控制器模块之间的通信链路的通信总线。通信总线包括多路复用器，其包括输出和输入，其从与控制器模块相关联的N个寄存器中选择的一个寄存器接收数据，并将数据传播到输出端，M地址寄存器存储多达N个N个地址的地址寄存器，M个数据寄存器，其接收与来自N个寄存器的M个的输出中的数据相对应的预取数据;以及第二多路复用器，其包括第二输出并且从M个数据寄存器读取预取数据并将预取数据传播到第二输出。 M和N是大于2的正整数，N大于M.

7. 发明授权

US06329938B1 Programmable analog-to-digital converter with bit conversion optimization 有权
标题翻译：具有位转换优化的可编程模数转换器
公开(公告)号：US06329938B1
公开(公告)日：2001-12-11
申请号：US09595437
申请日：2000-06-15
申请人： Michael R. Spaur , Francis M. Caster, II
发明人： Michael R. Spaur , Francis M. Caster, II
IPC分类号： H03M106
CPC分类号： H03M1/462 , H03M1/004
摘要： The present invention provides a programmable ADC with bit conversion optimization and method therefor. The programmable ADC includes an amplifier, a programmable clock generator, a comparator, a successive approximation logic, a digital-to-analog converter, and a voltage converter. The amplifier is arranged to sample and hold an input analog signal to be converted into N digital data bits. The programmable clock generator generates a clock signal for each of the N-bits to trigger setting of one of the N-bit digital data bits such that each of the N bits is set during a time optimized for each bit. The comparator is coupled to receive and compare the input analog signal with a successively approximated analog signal to generate a digital output signal. The successive approximation logic is configured to successively set each of the N-bits in response to the digital output signal and the clock signal to generate a successively approximated N-bit digital data. The digital-to-analog converter converts the successively approximated N-bit digital data into a successively approximated analog current signal. The voltage converter has a resistance value for converting the successively approximated analog current signals into the successively approximated analog signal for input to the comparator. The voltage converter is arranged to optimize a time constant defined by the resistance and an output capacitance of the digital-to-analog converter.
摘要翻译：本发明提供一种具有比特转换优化的可编程ADC及其方法。可编程ADC包括放大器，可编程时钟发生器，比较器，逐次逼近逻辑，数模转换器和电压转换器。放大器被设置为采样和保持输入模拟信号以被转换成N个数字数据位。可编程时钟发生器为每个N位产生时钟信号，以触发N位数字数据位之一的设置，使得在针对每个位优化的时间内设置每个N位。比较器被耦合以接收和比较输入的模拟信号与相继近似的模拟信号以产生数字输出信号。逐次逼近逻辑被配置为响应于数字输出信号和时钟信号连续设置每个N位以产生连续近似的N位数字数据。数模转换器将连续近似的N位数字数据转换为连续近似的模拟电流信号。电压转换器具有用于将连续逼近的模拟电流信号转换为连续逼近的模拟信号以输入到比较器的电阻值。电压转换器被布置成优化由电阻和数模转换器的输出电容定义的时间常数。

8. 发明授权

US4868482A CMOS integrated circuit having precision resistor elements 失效
标题翻译： CMOS集成电路具有精密电阻元件
公开(公告)号：US4868482A
公开(公告)日：1989-09-19
申请号：US104398
申请日：1987-10-05
申请人： Timothy G. O'Shaughnessy , Michael R. Spaur , Kenneth W. Ouyang
发明人： Timothy G. O'Shaughnessy , Michael R. Spaur , Kenneth W. Ouyang
IPC分类号： H03F3/345 , H03H11/46
CPC分类号： H03F3/345 , H03H11/46
摘要： A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.
摘要翻译：提供一种电路，用于通过感测参考电阻器在集成电路上实现多个精密电阻器元件。该电路包含第一电流源，该第一电流源使第一电流通过位于集成电路的导通或关闭的参考电阻以产生参考电压。参考电压施加到精密高增益运算放大器的反相输入端。第二电流源连接到在其欧姆区工作的第一MOS晶体管的漏极。第二电流源也连接到高增益运算放大器的非反相输入。运算放大器的输出电连接到第一和第二MOS晶体管的栅极。在操作中，跨第二MOS晶体管产生精密电阻，其等于或定位在芯片上或芯片上的参考精密电阻器的电阻的一些可确定的倍数。还公开了适用于该电路的运算放大器。

9. 发明授权

US07975110B1 Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers 有权
标题翻译：使用嵌入式磁盘控制器中的串行端口控制器支持多个外部串行端口设备的方法和系统
公开(公告)号：US07975110B1
公开(公告)日：2011-07-05
申请号：US11384657
申请日：2006-03-20
申请人： Michael R. Spaur , Ihn Kim
发明人： Michael R. Spaur , Ihn Kim
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0658 , G06F3/0683
摘要： A servo controller for a disk drive controller comprising a storage device that stores communication information for a plurality of devices and a serial port controller located on the servo controller that communicates with the storage device, that receives a request to communicate with one of the plurality of devices, and that allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.
摘要翻译：一种用于磁盘驱动器控制器的伺服控制器，包括存储装置，该存储装置存储用于多个装置的通信信息和位于与所述存储装置通信的所述伺服控制器上的串行端口控制器，所述串行端口控制器接收与所述多个装置之一通信的请求设备，并且其允许根据所存储的通信信息和所述请求在至少一个处理器与所述多个设备中的一个之间进行通信，其中所述多个设备中的每一个使用不同的协议。

10. 发明申请

US20090097157A1 METHOD AND SYSTEM FOR HEAD POSITION CONTROL IN EMBEDDED DISK DRIVE CONTROLLERS 有权
标题翻译：嵌入式磁盘驱动控制器的头位置控制方法与系统
公开(公告)号：US20090097157A1
公开(公告)日：2009-04-16
申请号：US12338071
申请日：2008-12-18
申请人： Michael R. Spaur , Raymond A. Sandoval
发明人： Michael R. Spaur , Raymond A. Sandoval
IPC分类号： G11B5/596
CPC分类号： G11B5/59655 , G11B5/59605
摘要： A track follow controller includes a burst selector selecting at least one burst pair based on burst pair selection data. A linear position calculator calculates a primary head position and a secondary head position based on the at least one burst pair, and calculates a head linear position based on the primary head position and the secondary head position.
摘要翻译：轨道跟随控制器包括基于突发组选择数据选择至少一个脉冲串对的突发选择器。线性位置计算器基于至少一个突发对来计算主要头部位置和次要头部位置，并且基于主要头部位置和次要头部位置来计算头部线性位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式