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1. 发明申请

US20160179611A1 LOW OVERHEAD ERROR CHECKING AND CORRECTION APPARATUS AND METHOD 审中-公开
标题翻译： LOW OVERHEAD ERROR CHECKING AND CORRECTION设备和方法
公开(公告)号：US20160179611A1
公开(公告)日：2016-06-23
申请号：US14581878
申请日：2014-12-23
申请人： Thuyen Le , Kay Hesse , Uwe Steeb , Tian Yan Pu , Lars Melzer
发明人： Thuyen Le , Kay Hesse , Uwe Steeb , Tian Yan Pu , Lars Melzer
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.
摘要翻译：描述了用于执行低开销错误检查和校正的装置和方法。例如，电子电路的一个实施例包括：用于以行和列存储数据或指令的一个或多个存储器，并且还用于存储包括与每行和列奇偶校验数据相关联的奇偶校验值的行奇偶校验数据，其包括与每列; 以及错误检查逻辑来执行行奇偶校验以检测是否存在任何行中的错误，其中如果在其中一行中检测到错误，则错误检查和校正逻辑是执行列奇偶校验以识别列其中检测到的错误发生; 以及纠错逻辑，以使用由错误检查逻辑识别的检测到的行和列校正检测到的错误。

2. 发明申请

US20160259397A1 INTEGRATED CIRCUIT WITH ON-CHIP POWER PROFILING 有权
标题翻译：集成电路与片上电源配置
公开(公告)号：US20160259397A1
公开(公告)日：2016-09-08
申请号：US14635607
申请日：2015-03-02
申请人： Tian Yan Pu , Chenbo Liu , Thuyen Le , Lars Melzer
发明人： Tian Yan Pu , Chenbo Liu , Thuyen Le , Lars Melzer
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F11/2273
摘要： Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.
摘要翻译：实施例包括用于确定集成电路中的电路块的功耗的装置，方法和系统。集成电路可以包括第一和第二电源网络。在一些实施例中，集成电路可以包括被测电路块的多个实例。电路块的第一实例可以在第一测试运行期间耦合到第一电源网络，并且在第二测试运行期间电路块的第二实例可耦合到第二电源网络。在其他实施例中，被测电路块的单个实例可以在第一测试运行期间与第一电源网络耦合，并且在第二测试运行期间与第二电源网络耦合。可以基于第一和第二测试运行来确定电路块的功耗。

3. 发明授权

US08055931B2 Method for switching between two redundant oscillator signals within an alignment element 有权
标题翻译：用于在对准元件内切换两个冗余振荡器信号的方法
公开(公告)号：US08055931B2
公开(公告)日：2011-11-08
申请号：US12246123
申请日：2008-10-06
申请人： Ralf Ludewig , Thuyen Le , Tilman Gloekler , Willm Hinrichs
发明人： Ralf Ludewig , Thuyen Le , Tilman Gloekler , Willm Hinrichs
IPC分类号： G06F1/04
CPC分类号： G06F1/12
摘要： A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.
摘要翻译：提供了一种用于在对准元件内的两个振荡器信号之间切换的方法。根据该方法，选择两个振荡器信号之一作为第一主信号，以便在对准元件的输出处提供输出步进信号。该方法包括当两个振荡器信号之间的开关发生时或当检测到第一主信号的故障时引入虚拟步进信号。该方法还包括在开关的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成。

4. 发明申请

US20100182916A1 SYSTEM AND METHOD FOR OPTIMIZING NETWORK WIRELESS COMMUNICATION RESOURCES 有权
标题翻译：用于优化网络无线通信资源的系统和方法
公开(公告)号：US20100182916A1
公开(公告)日：2010-07-22
申请号：US12357429
申请日：2009-01-22
申请人： Christian Drewes , Markus Mueck , Thuyen Le , Hyung-Nam Choi
发明人： Christian Drewes , Markus Mueck , Thuyen Le , Hyung-Nam Choi
IPC分类号： H04L12/66 , H04B7/14
CPC分类号： H04W28/00 , H04B7/15521 , H04B7/2606 , H04L1/0017 , H04L1/004 , H04L2001/0097 , H04W24/02 , H04W88/04
摘要： Embodiments are described that provide methods and radio networks that communicate data between a mobile communication device and a core network. The methods include using network coding to encode data, and communicating a subset of the encoded data between the mobile communication device and the core network through a dynamic relay station.
摘要翻译：描述了提供在移动通信设备和核心网络之间传送数据的方法和无线电网络的实施例。这些方法包括使用网络编码来对数据进行编码，以及通过动态中继站在移动通信设备和核心网络之间传送编码数据的子集。

5. 发明申请

US20080209245A1 Accounting for Microprocessor Resource Consumption 失效
标题翻译：计算微处理器资源消耗
公开(公告)号：US20080209245A1
公开(公告)日：2008-08-28
申请号：US12029636
申请日：2008-02-12
申请人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
发明人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
IPC分类号： G06F1/06 , G06F1/32
CPC分类号： G06F11/3058 , G06F11/3024 , G06F11/3419 , G06F11/348
摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.
摘要翻译：用于会计微处理器资源消耗的技术。本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

6. 发明申请

US20050207479A1 Method and device for carrying out a plurality of correlation procedures in a mobile telephony environment 有权
标题翻译：用于在移动电话环境中执行多个相关程序的方法和装置
公开(公告)号：US20050207479A1
公开(公告)日：2005-09-22
申请号：US11075848
申请日：2005-03-09
申请人： Thomas Ruprich , Steffen Paul , Burkhard Becker , Thuyen Le , Manfred Zimmermann , Christian Drewes
发明人： Thomas Ruprich , Steffen Paul , Burkhard Becker , Thuyen Le , Manfred Zimmermann , Christian Drewes
IPC分类号： G06F17/15 , H04B1/707
CPC分类号： G06F17/15 , H04B1/707
摘要： In a method for carrying out a plurality of correlation procedures in a mobile radio system, sample values which have been written to a data memory (DS) are read using a predetermined reading rule. Two correlation procedures are carried out on the basis of the sample values which have been read. This reading rule is in this case independent of the correlation procedure to be carried out.
摘要翻译：在用于在移动无线电系统中执行多个相关程序的方法中，使用预定的读取规则读取已写入数据存储器（DS）的样本值。基于所读取的样本值进行两个相关程序。在这种情况下，这种阅读规则独立于要执行的相关程序。

7. 发明申请

US20050195926A1 Device and method for carrying out correlations in a mobile radio system 审中-公开
标题翻译：在移动无线电系统中执行相关的装置和方法
公开(公告)号：US20050195926A1
公开(公告)日：2005-09-08
申请号：US11076094
申请日：2005-03-09
申请人： Thomas Ruprich , Steffen Paul , Burkhard Becker , Thuyen Le
发明人： Thomas Ruprich , Steffen Paul , Burkhard Becker , Thuyen Le
IPC分类号： H04B1/707 , H04L27/06
CPC分类号： H04L27/06 , H04B1/70735 , H04B1/70752 , H04B1/708 , H04B2201/70707
摘要： A device (11) for carrying out a correlation, having a data memory (12) for storage of a sequence of sample values (110), having an address generator (13) for production of addresses for reading a data word (111), in which the sequence of sample values in the data word (111) need not be chronological, having a code generator (15) for production of a correlation word (112) from sequence elements in a correlation sequence, with the sequence elements being arranged in the correlation word (112) in a sequence which depends on the data word (111), and having a correlator unit (14).
摘要翻译：一种用于执行相关性的设备（11），具有用于存储采样值序列（110）的数据存储器（12），具有用于产生用于读取数据字（111）的地址的地址发生器（13）其中数据字（111）中的采样值的序列不需要按时间顺序，具有用于从相关序列中的序列元素产生相关字（112）的代码发生器（15），其中序列元素被布置在取决于数据字（111）的序列中的相关字（112），并具有相关器单元（14）。

8. 发明授权

US08514790B2 System and method for optimizing network wireless communication resources 有权
标题翻译：优化网络无线通信资源的系统和方法
公开(公告)号：US08514790B2
公开(公告)日：2013-08-20
申请号：US12357429
申请日：2009-01-22
申请人： Christian Drewes , Markus Mueck , Thuyen Le , Hyung-Nam Choi
发明人： Christian Drewes , Markus Mueck , Thuyen Le , Hyung-Nam Choi
IPC分类号： H04W4/00 , H04L12/28
CPC分类号： H04W28/00 , H04B7/15521 , H04B7/2606 , H04L1/0017 , H04L1/004 , H04L2001/0097 , H04W24/02 , H04W88/04
摘要： Embodiments are described that provide methods and radio networks that communicate data between a mobile communication device and a core network. The methods include using network coding to encode data, and communicating a subset of the encoded data between the mobile communication device and the core network through a dynamic relay station.
摘要翻译：描述了提供在移动通信设备和核心网络之间通信数据的方法和无线电网络的实施例。所述方法包括使用网络编码来对数据进行编码，以及通过动态中继站在移动通信设备和核心网络之间传送编码数据的子集。

9. 发明授权

US07877655B2 Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit 失效
标题翻译：在集成电路上使用LBIST引擎执行测试用例的方法，用于指定集成电路的集成电路和方法
公开(公告)号：US07877655B2
公开(公告)日：2011-01-25
申请号：US11855505
申请日：2007-09-14
申请人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
发明人： Thuyen Le , Thomas Pflueger , Martin Padeffke , Stefan Bonsels
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/318502
摘要： A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.
摘要翻译：一种在具有根据预定方案互连的多个存储元件和逻辑电路的集成电路上的至少一个LBIST引擎执行测试用例的方法。 LBIST引擎部分由存储元件和/或逻辑电路构成。至少一个扫描链形成为一系列所选择的存储元件，并且其它存储元件用于LBIST引擎或在测试模式中用于所述LBIST引擎的一部分。扫描链由测试模式驱动，LBIST测试用例正在测试对应于所述扫描链的存储元件的逻辑电路的那些部分。

10. 发明授权

US07788432B2 System for performing a serial communication between a central control block and satellite components 有权
标题翻译：用于执行中央控制块和卫星组件之间的串行通信的系统
公开(公告)号：US07788432B2
公开(公告)日：2010-08-31
申请号：US12244430
申请日：2008-10-02
申请人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
发明人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
IPC分类号： G06F13/00
CPC分类号： G06F13/4286
摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.
摘要翻译：这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间执行串行通信的系统。该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。该系统还包括集中式定时器。卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。实施单包络交易。与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。

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