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1. 发明申请

US20120079146A1 METHOD AND ARRANGEMENT FOR STREAMING DATA PROFILING 失效
标题翻译：流动数据分析的方法和布置
公开(公告)号：US20120079146A1
公开(公告)日：2012-03-29
申请号：US13245899
申请日：2011-09-27
申请人： Kay HESSE
发明人： Kay HESSE
IPC分类号： G06F13/42
CPC分类号： G06F13/385 , G06F11/349
摘要： A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.
摘要翻译：电路装置包括多个功能单元，每个功能单元包括多个数据处理模块和本地控制器。多个数据处理模块运行公共系统时钟，并通过运行握手型流数据传输协议的流数据总线进行连接。电路装置的分析模块评估在实时操作期间在流数据总线的预定接口处被抽头的控制信号，用于确定用于分析和调试目的的链路性能和通信模式，并且因此构成用于评估帧内编码的简单和低成本的方法，组件和组件间链路性能和大型SoC上的通信模式。还提供了一种用于对这种电路装置使用的数据流进行分析的方法。

2. 发明申请

US20120072789A1 MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY CONFIGURED TO FACILITATE PRODUCTION OF PRE-STRESSED INTEGRATED CIRCUITS AND METHODS 有权
标题翻译：内存自检（MBIST）电路配置，以便于生产预应力集成电路和方法
公开(公告)号：US20120072789A1
公开(公告)日：2012-03-22
申请号：US12883450
申请日：2010-09-16
申请人： Wei-Yu Chen , Kevin Badgett , Kay Hesse
发明人： Wei-Yu Chen , Kevin Badgett , Kay Hesse
IPC分类号： G11C29/12 , G06F11/00
CPC分类号： G11C29/06 , G11C29/28 , G11C2029/2602
摘要： Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.
摘要翻译：具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。在本发明的一个方面中，使用MBST电路将阵列的存储器元件设置为第一状态，然后在老化操作期间处于反向状态，以将两个相对状态中的每一个保持期望的时间，以便强制a 集成电路部件故障或产生超过初级阶段的预应力部件。优选地，提供具有MIBST电路的集成电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。

3. 发明授权

US07653845B2 Test algorithm selection in memory built-in self test controller 有权
标题翻译：内存测试控制器内置测试算法选择
公开(公告)号：US07653845B2
公开(公告)日：2010-01-26
申请号：US11484157
申请日：2006-07-11
申请人： Siegfried Kay Hesse , Markus Seuring , Thomas Herrmann
发明人： Siegfried Kay Hesse , Markus Seuring , Thomas Herrmann
IPC分类号： G11C29/00
CPC分类号： G11C29/16
摘要： An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.
摘要翻译：提供了一种集成电路芯片，其包括片上存储器和测试电路。测试电路被配置为执行片上存储器的操作测试。测试电路包括控制器，其被配置为执行从多个测试算法中的选择以执行操作测试。多个测试算法包括故障检测测试算法，以对片内存储器进行操作测试，以便检测是否存在存储器故障，而不定位存储器故障。多个测试算法还包括故障定位测试算法，以执行片上存储器的操作测试，以便检测和定位存储器故障。此外，提供了执行存储器内置自检和MBIST（存储器内置自检）控制电路模板的方法。

4. 发明授权

US07194583B2 Controlling the replacement of prefetched descriptors in a cache 有权
标题翻译：控制高速缓存中预取描述符的替换
公开(公告)号：US07194583B2
公开(公告)日：2007-03-20
申请号：US10464966
申请日：2003-06-19
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/121
摘要： A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.
摘要翻译：提供了诸如南桥的USB主机控制器的主机控制器以及相应的操作方法。主机控制器包括描述符提取单元，其适于发送对描述符的请求并且接收描述符以回复请求。描述符是用于描述从主机控制器控制的设备传输数据的属性的数据结构。主机控制器还包括适于存储预取描述符的描述符高速缓存。所述描述符缓存进一步适于存储所存储的预取描述符的至少一部分的各个替换控制值。主机控制器被设置为基于与所存储的预取描述符相关联的替换控制值，用新的预取描述符替换描述符高速缓存中存储的预取描述符。替代技术可以提高主机控制器操作的整体效率。

5. 发明申请

US20060095642A1 USB on-the-go controller 有权
标题翻译： USB即插即用控制器
公开(公告)号：US20060095642A1
公开(公告)日：2006-05-04
申请号：US11230979
申请日：2005-09-20
申请人： Kay Hesse , Sven Mueller
发明人： Kay Hesse , Sven Mueller
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine partly in hardware and partly in software. The OTG control unit may have an OTG control register and an OTG status register which are accessible by software. Further, the USB controller device may have a device control unit to implement device functionality and a port multiplexer to assign a physical port to either the host or the device control unit. The OTG control unit may be comprised in the port multiplexer. Further, a software driver may read the OTG status register in response to receiving an interrupt from the USB controller device, and write to the OTG control register to force the USB controller device to change its OTG state.
摘要翻译：提供了一种实现OTG（On-The-Go）功能的USB（通用串行总线）控制器技术。该设备可以具有兼容EHCI（增强型主机控制器接口）的主机控制单元，以及OTG控制单元，部分以硬件部分实现OTG状态机部分软件。 OTG控制单元可以具有可由软件访问的OTG控制寄存器和OTG状态寄存器。此外，USB控制器设备可以具有实现设备功能的设备控制单元和端口复用器以将物理端口分配给主机或设备控制单元。 OTG控制单元可以包括在端口复用器中。此外，软件驱动程序可以响应于从USB控制器设备接收中断而读取OTG状态寄存器，并写入OTG控制寄存器以迫使USB控制器设备改变其OTG状态。

6. 发明授权

US06990550B2 Transaction duration management in a USB host controller 有权
公开(公告)号：US06990550B2
公开(公告)日：2006-01-24
申请号：US10283555
申请日：2002-10-30
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F13/20 , H04J3/16
CPC分类号： G06F13/1605
摘要： A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

7. 发明授权

US06944725B2 Reciprocally adjustable dual queue mechanism 失效
标题翻译：相互可调的双排队机制
公开(公告)号：US06944725B2
公开(公告)日：2005-09-13
申请号：US10283733
申请日：2002-10-30
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00 , G06F13/38
CPC分类号： G06F13/385 , G06F3/0601 , G06F2003/0691 , G06F2213/0042
摘要： A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.
摘要翻译：提供了一种数据存储机制，其中多个数据项被存储在多个寄存器元件中。每个注册的元素能够存储至少一个数据项。多个寄存器元件被布置成形成寄存器元件的序列。第一数据存储在序列的第一部分中，第二数据被存储在序列的第二部分中。第一部分和第二部分是可变长度，其可变长度之和等于寄存器元件序列的长度。因此，提供了一种双端口队列机制，其可以用于存储周期性地或异步地调度的不同类型或数据的数据。该机制可用于兼容USB 2.0的主机控制器。

8. 发明授权

US06823403B2 DMA mechanism for high-speed packet bus 有权
标题翻译： DMA机制用于高速分组总线
公开(公告)号：US06823403B2
公开(公告)日：2004-11-23
申请号：US10184407
申请日：2002-06-27
申请人： Dale E. Gulick , Siegfried Kay Hesse
发明人： Dale E. Gulick , Siegfried Kay Hesse
IPC分类号： G06F1328
CPC分类号： G06F12/0879 , G06F13/28 , H04B7/0822
摘要： A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.
摘要翻译：提供了DMA（直接存储器访问）机制，其可以具有改进的性能，特别是与高速分组总线相关。一种用于输出对存储器接口的读取请求并从存储器接口接收所请求的数据的发送DMA引擎，包括用于输出识别第一存储器范围的第一地址数据的数据传输启动单元。此外，提供边界对齐单元，用于使用第一地址数据生成第二地址数据，其中第二地址数据标识与至少一个边界中的第一存储器范围不同的第二存储器范围。此外，可以在接收DMA引擎中进行相应的边界对准。 DMA机制可以在具有HyperTransport功能的USB-2主机控制器中执行。

9. 发明申请

US20160179611A1 LOW OVERHEAD ERROR CHECKING AND CORRECTION APPARATUS AND METHOD 审中-公开
标题翻译： LOW OVERHEAD ERROR CHECKING AND CORRECTION设备和方法
公开(公告)号：US20160179611A1
公开(公告)日：2016-06-23
申请号：US14581878
申请日：2014-12-23
申请人： Thuyen Le , Kay Hesse , Uwe Steeb , Tian Yan Pu , Lars Melzer
发明人： Thuyen Le , Kay Hesse , Uwe Steeb , Tian Yan Pu , Lars Melzer
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.
摘要翻译：描述了用于执行低开销错误检查和校正的装置和方法。例如，电子电路的一个实施例包括：用于以行和列存储数据或指令的一个或多个存储器，并且还用于存储包括与每行和列奇偶校验数据相关联的奇偶校验值的行奇偶校验数据，其包括与每列; 以及错误检查逻辑来执行行奇偶校验以检测是否存在任何行中的错误，其中如果在其中一行中检测到错误，则错误检查和校正逻辑是执行列奇偶校验以识别列其中检测到的错误发生; 以及纠错逻辑，以使用由错误检查逻辑识别的检测到的行和列校正检测到的错误。

10. 发明申请

US20130205104A1 Finite State Machine for System Management 有权
标题翻译：系统管理有限状态机
公开(公告)号：US20130205104A1
公开(公告)日：2013-08-08
申请号：US13763614
申请日：2013-02-08
申请人： Kay HESSE
发明人： Kay HESSE
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G05B19/045 , G05B2219/23289 , G06F9/4498
摘要： Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.
摘要翻译：实现涉及基于微编码处理器的混合有限状态机和使用查找表来实现组合逻辑。微编码用于描述FSM的状态转换，查找表用于确定状态转换的条件，并根据状态生成输出。

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