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1. 发明授权

US07788432B2 System for performing a serial communication between a central control block and satellite components 有权
标题翻译：用于执行中央控制块和卫星组件之间的串行通信的系统
公开(公告)号：US07788432B2
公开(公告)日：2010-08-31
申请号：US12244430
申请日：2008-10-02
申请人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
发明人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
IPC分类号： G06F13/00
CPC分类号： G06F13/4286
摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.
摘要翻译：这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间执行串行通信的系统。该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。该系统还包括集中式定时器。卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。实施单包络交易。与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。

2. 发明申请

US20090113094A1 System for performing a serial communication between a central control block and satellite components 有权
标题翻译：用于执行中央控制块和卫星组件之间的串行通信的系统
公开(公告)号：US20090113094A1
公开(公告)日：2009-04-30
申请号：US12244430
申请日：2008-10-02
申请人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
发明人： Ralf Ludewig , Thuyen Le , Tobias Webel , Klaus Peter Gungl
IPC分类号： G06F13/00
CPC分类号： G06F13/4286
摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.
摘要翻译：这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间进行串行通信的系统。该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。该系统还包括集中式定时器。卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。实施单包络交易。与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。

3. 发明申请

US20080209245A1 Accounting for Microprocessor Resource Consumption 失效
标题翻译：计算微处理器资源消耗
公开(公告)号：US20080209245A1
公开(公告)日：2008-08-28
申请号：US12029636
申请日：2008-02-12
申请人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
发明人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
IPC分类号： G06F1/06 , G06F1/32
CPC分类号： G06F11/3058 , G06F11/3024 , G06F11/3419 , G06F11/348
摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.
摘要翻译：用于会计微处理器资源消耗的技术。本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

4. 发明授权

US08140885B2 Accounting for microprocessor resource consumption 失效
标题翻译：计算微处理器资源消耗
公开(公告)号：US08140885B2
公开(公告)日：2012-03-20
申请号：US12029636
申请日：2008-02-12
申请人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
发明人： Daniel Becker , Rafael Keggenhoff , Thuyen Le , Tobias Webel , Matthias Woehrle
IPC分类号： G06F1/08
CPC分类号： G06F11/3058 , G06F11/3024 , G06F11/3419 , G06F11/348
摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.
摘要翻译：用于会计微处理器资源消耗的技术。本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

5. 发明授权

US08479070B2 Integrated circuit arrangement for test inputs 有权
标题翻译：用于测试输入的集成电路布置
公开(公告)号：US08479070B2
公开(公告)日：2013-07-02
申请号：US12822287
申请日：2010-06-24
申请人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
发明人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
IPC分类号： G01R31/28
CPC分类号： G01R31/31701 , G01R31/3172
摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要翻译：集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

6. 发明申请

US20110320898A1 Integrated Circuit Arrangement For Test Inputs 有权
标题翻译：用于测试输入的集成电路布置
公开(公告)号：US20110320898A1
公开(公告)日：2011-12-29
申请号：US12822287
申请日：2010-06-24
申请人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
发明人： Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31701 , G01R31/3172
摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要翻译：集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

7. 发明授权

US08868960B2 Synchronous clock stop in a multi nodal computer system 有权
标题翻译：多节点计算机系统中的同步时钟停止
公开(公告)号：US08868960B2
公开(公告)日：2014-10-21
申请号：US13170466
申请日：2011-06-28
申请人： Tobias Bergmann , Ralf Ludewig , Tobias Webel , Ulrich Weiss
发明人： Tobias Bergmann , Ralf Ludewig , Tobias Webel , Ulrich Weiss
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16 , G06F1/32
CPC分类号： G06F1/12 , G06F1/3237 , Y02D10/128
摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.
摘要翻译：提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。在运行中，偏移计数器由参考时钟同步。

8. 发明授权

US07966536B2 Method and apparatus for automatic scan completion in the event of a system checkstop 失效
标题翻译：在系统检查停止的情况下自动扫描完成的方法和装置
公开(公告)号：US07966536B2
公开(公告)日：2011-06-21
申请号：US12101208
申请日：2008-04-11
申请人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
发明人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/0784 , G06F11/0706 , G06F11/0778 , G06F11/2236
摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.
摘要翻译：在处理器中系统检查停止时自动扫描完成的方法。处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里如果没有发生系统检查停止，则已存储。

9. 发明申请

US20090259899A1 METHOD AND APPARATUS FOR AUTOMATIC SCAN COMPLETION IN THE EVENT OF A SYSTEM CHECKSTOP 失效
标题翻译：在系统检查中的自动扫描完成的方法和装置
公开(公告)号：US20090259899A1
公开(公告)日：2009-10-15
申请号：US12101208
申请日：2008-04-11
申请人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
发明人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
IPC分类号： G01R31/28
CPC分类号： G06F11/0784 , G06F11/0706 , G06F11/0778 , G06F11/2236
摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.
摘要翻译：在处理器中系统检查停止时自动扫描完成的方法。处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里如果没有发生系统检查停止，则已存储。

10. 发明授权

US07996715B2 Multi nodal computer system and method for handling check stops in the multi nodal computer system 有权
标题翻译：多节点计算机系统和多节点计算机系统中检查停止处理方法
公开(公告)号：US07996715B2
公开(公告)日：2011-08-09
申请号：US12265137
申请日：2008-11-05
申请人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas E. Gilbert , Timothy G. McNamara , Patrick J. Meaney
发明人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas E. Gilbert , Timothy G. McNamara , Patrick J. Meaney
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/544 , G06F11/0709 , Y10S707/99931 , Y10S707/99939 , Y10S707/99943
摘要： A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.
摘要翻译：一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。

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