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1. 发明授权

US07598572B2 Silicided polysilicon spacer for enhanced contact area 失效
标题翻译：用于增强接触面积的硅化多晶硅间隔物
公开(公告)号：US07598572B2
公开(公告)日：2009-10-06
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L29/40
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

2. 发明申请

US20080102612A1 SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA 失效
标题翻译：用于增强接触面积的多孔聚硅氧烷绝缘子
公开(公告)号：US20080102612A1
公开(公告)日：2008-05-01
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L21/44 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

3. 发明授权

US07393746B2 Post-silicide spacer removal 失效
标题翻译：后硅化物间隔物去除
公开(公告)号：US07393746B2
公开(公告)日：2008-07-01
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
IPC分类号： H01L21/33
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
摘要翻译：一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。然后，该方法在衬底的暴露区域的表面上形成硅化物。该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

4. 发明申请

US20080090370A1 Post-silicide spacer removal 失效
公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

5. 发明授权

US07541288B2 Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques 有权
标题翻译：使用绝缘体沉积和绝缘体间隙填充技术形成集成电路结构的方法
公开(公告)号：US07541288B2
公开(公告)日：2009-06-02
申请号：US11683590
申请日：2007-03-08
申请人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
发明人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
IPC分类号： H01L21/311
CPC分类号： H01L21/0217 , C23C16/56 , H01L21/02211 , H01L21/02266 , H01L21/02274 , H01L21/31051 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76837 , H01L21/823425
摘要： Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.
摘要翻译：形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，其包括至少一个峰和至少一个与该至少一个峰相邻的谷。然后进行非均匀的增稠步骤。这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

6. 发明授权

US07317204B2 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US07317204B2
公开(公告)日：2008-01-08
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

7. 发明申请

US20080220584A1 Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques 有权
标题翻译：使用绝缘体沉积和绝缘子间隙填充技术形成集成电路结构的方法
公开(公告)号：US20080220584A1
公开(公告)日：2008-09-11
申请号：US11683590
申请日：2007-03-08
申请人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
发明人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
IPC分类号： H01L29/82
CPC分类号： H01L21/0217 , C23C16/56 , H01L21/02211 , H01L21/02266 , H01L21/02274 , H01L21/31051 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76837 , H01L21/823425
摘要： Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.
摘要翻译：形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，该电绝缘层包括至少一个峰和至少与至少一个峰相邻的峰。然后进行非均匀的增稠步骤。这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

8. 发明申请

US20060163569A1 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US20060163569A1
公开(公告)日：2006-07-27
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

9. 发明授权

US07923365B2 Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon 有权
标题翻译：在其上形成具有应力诱导侧壁绝缘间隔物的场效应晶体管的方法
公开(公告)号：US07923365B2
公开(公告)日：2011-04-12
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

10. 发明授权

US07863693B2 Forming conductive stud for semiconductive devices 有权
标题翻译：形成用于半导体器件的导电螺柱
公开(公告)号：US07863693B2
公开(公告)日：2011-01-04
申请号：US12013622
申请日：2008-01-14
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/02
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.
摘要翻译：本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻通过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。本发明的实施例还提供由其制成的半导体器件。

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