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1. 发明授权

US06172390B2 Semiconductor device with vertical transistor and buried word line 失效
标题翻译：半导体器件采用垂直晶体管和掩埋字线
公开(公告)号：US06172390B2
公开(公告)日：2001-01-09
申请号：US09047581
申请日：1998-03-25
申请人： Thomas S. Rupp , Johann Alsmeier
发明人： Thomas S. Rupp , Johann Alsmeier
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.
摘要翻译：字线埋在垂直半导体器件旁边。字线被嵌入与垂直半导体器件相邻，使得字线的形貌基本上是平面的。掩埋字线的平面特征允许在字线和垂直晶体管上执行进一步处理。在另一个实施例中，垂直半导体器件是具有垂直取向栅极的晶体管。字线被埋在垂直取向的栅极旁边，使得字线的形状基本上是平面的。

2. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

3. 发明授权

US6091094A Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips 失效
标题翻译：与字线侧壁相邻形成的垂直器件和用于半导体芯片的方法
公开(公告)号：US6091094A
公开(公告)日：2000-07-18
申请号：US95793
申请日：1998-06-11
申请人： Thomas S. Rupp
发明人： Thomas S. Rupp
IPC分类号： H01L21/82 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.
摘要翻译：半导体器件包括形成沟槽的衬底，沟槽包括设置在沟槽内的存储节点。字线设置在衬底内并与衬底的一部分相邻。包括垂直布置的晶体管，其中字线用作栅极，存储节点和作为源极和漏极之一的位线功能，使得当由字线激活时，晶体管在存储节点和位线之间导通。本发明还包括一种制造具有垂直晶体管的半导体器件的方法。

4. 发明授权

US06699750B1 Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips 失效
标题翻译：与字线侧壁相邻形成的垂直器件和用于半导体芯片的方法
公开(公告)号：US06699750B1
公开(公告)日：2004-03-02
申请号：US09145623
申请日：1998-09-02
申请人： Thomas S. Rupp
发明人： Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.
摘要翻译：半导体器件包括形成沟槽的衬底，沟槽包括设置在沟槽内的存储节点。字线设置在衬底内并与衬底的一部分相邻。包括垂直布置的晶体管，其中字线用作栅极，存储节点和作为源极和漏极之一的位线功能，使得当由字线激活时，晶体管在存储节点和位线之间导通。本发明还包括一种制造具有垂直晶体管的半导体器件的方法。

5. 发明授权

US06960523B2 Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device 失效
标题翻译：在DRAM器件的位线接触的氮化物衬垫层的反应离子蚀刻期间减少氮化物栅极帽层的侵蚀的方法
公开(公告)号：US06960523B2
公开(公告)日：2005-11-01
申请号：US10406645
申请日：2003-04-03
申请人： Michael Maldei , Prakash C. Dev , David Dobuzinsky , Johnathan Faltermeier , Thomas S. Rupp , Chienfan Yu , Rajesh Rengarajan , John Benedict , Munir-ud-Din Naeem
发明人： Michael Maldei , Prakash C. Dev , David Dobuzinsky , Johnathan Faltermeier , Thomas S. Rupp , Chienfan Yu , Rajesh Rengarajan , John Benedict , Munir-ud-Din Naeem
IPC分类号： H01L21/311 , H01L21/60 , H01L21/8242 , H01L23/485 , H01L21/4763 , H01L21/3205
CPC分类号： H01L27/10888 , H01L21/31116 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.
摘要翻译：相对于氮化物盖层的蚀刻速率，氮化物衬垫层的蚀刻速率得以改善。氮化物衬垫层位于衬底附近的位于衬底顶部的堆叠结构的暴露部分。氮化物覆盖层位于堆叠结构的顶部。沿堆叠结构的侧壁形成氧化物间隔物。氮化物衬里层被图案化和蚀刻以在衬底中形成至少一个开口，而氮化物覆盖层基本保持不变。

6. 发明授权

US06255158B1 Process of manufacturing a vertical dynamic random access memory device 失效
标题翻译：制造垂直动态随机存取存储器件的过程
公开(公告)号：US06255158B1
公开(公告)日：2001-07-03
申请号：US09667652
申请日：2000-09-22
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域，在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体，具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

7. 发明授权

US06204187B1 Contact and deep trench patterning 有权
标题翻译：接触和深沟槽图案化
公开(公告)号：US06204187B1
公开(公告)日：2001-03-20
申请号：US09226434
申请日：1999-01-06
申请人： Thomas S. Rupp , Alan Thomas , Franz Zach
发明人： Thomas S. Rupp , Alan Thomas , Franz Zach
IPC分类号： H01L21311
CPC分类号： H01L21/31144 , H01L21/76229 , H01L21/76816
摘要： A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.
摘要翻译：用于图案化半导体部件的方法包括以下步骤：提供衬底层，其上形成有介电层的衬底层和形成在电介质层上的掩模层，掩模层可相对于电介质层选择性地蚀刻，图案化掩模层以在掩模层中形成第一组基本上平行的线，并且对该电介质层进行图案化以在基底层中形成矩形孔。还包括根据本发明的半导体器件。

8. 发明授权

US06486505B1 Semiconductor contact and method of forming the same 有权
标题翻译：半导体接触及其形成方法
公开(公告)号：US06486505B1
公开(公告)日：2002-11-26
申请号：US09535445
申请日：2000-03-24
申请人： Thomas S. Rupp , Jeffrey P. Gambino , Peter Hoh , Senthil Srinivasan
发明人： Thomas S. Rupp , Jeffrey P. Gambino , Peter Hoh , Senthil Srinivasan
IPC分类号： H01L27108
CPC分类号： H01L27/10873
摘要： In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.
摘要翻译：一方面，本发明公开了一种晶体管器件（参见例如图3），其包括设置在半导体本体122中并由通道区域128a隔开的第一和第二源极/漏极区域124a和126。电介质层134a覆盖在沟道区128a上，栅电极130a / 132a覆盖在电介质层134a上。在优选实施例中，栅电极包括在电介质层上延伸第一横向距离的多晶硅层130a和在第一多晶硅层上延伸第二横向距离的硅化物层132a。在该示例中，第一横向距离大于第二横向距离。

9. 发明授权

US06444531B1 Disposable spacer technology for device tailoring 有权
标题翻译：一次性间隔技术用于设备定制
公开(公告)号：US06444531B1
公开(公告)日：2002-09-03
申请号：US09645424
申请日：2000-08-24
申请人： Thomas S. Rupp , Scott Halle
发明人： Thomas S. Rupp , Scott Halle
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/823468 , H01L29/6659
摘要： The present provides a method for tailoring silicon dioxide source and drain implants and, if desired, extension implants of different devices used on a semiconductor wafer in order to realize shallow junctions and minimize the region of overlap between the gate and source and drain regions and any extension implants. The method includes the steps of applying a mask over a first gate structure positioned on a semiconductor substrate, depositing a layer of a spacer material over the surface of the first gate structure and a second gate structure adjacent to the first gate structure, etching the spacer material so that a portion of the spacer material remains on the second gate sidewalls and a sidewall of the block out mask, implanting ions into the semiconductor substrate into a region defined between the spacer material on the block out mask and the second gate to form a source or drain region, and removing the spacer material and block out mask. If desired, a second etch can be performed on the spacer material to reduce spacer thickness, and second ions can be implanted into the semiconductor substrate into an implant region defined between the spacer material remaining after the second etch.
摘要翻译：本发明提供了一种用于定制二氧化硅源和漏极注入的方法，并且如果需要，在半导体晶片上使用不同器件的延伸注入，以实现浅结并且使栅极和源极和漏极区之间的重叠区域最小化，以及任何延长种植体。该方法包括以下步骤：在位于半导体衬底上的第一栅极结构上施加掩模，在第一栅极结构的表面上沉积间隔材料层，以及邻近第一栅极结构的第二栅极结构，蚀刻间隔物材料，使得间隔物材料的一部分保留在第二栅极侧壁和阻挡掩模的侧壁上，将离子注入到半导体衬底中，形成限定在阻挡物掩模掩模上的间隔物材料和第二栅极之间的区域，以形成源极或漏极区域，并且去除间隔物材料并阻挡掩模。如果需要，可以对间隔物材料执行第二蚀刻以减少间隔物厚度，并且可以将第二离子注入到半导体衬底中的限定在第二蚀刻之后残留的间隔物材料之间的注入区域中。

10. 发明授权

US06274440B1 Manufacturing of cavity fuses on gate conductor level 失效
标题翻译：在栅极导体级制造腔体保险丝
公开(公告)号：US06274440B1
公开(公告)日：2001-08-14
申请号：US09282134
申请日：1999-03-31
申请人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
发明人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
摘要翻译：用于在栅极导体堆叠上形成腔体熔断器的结构和方法。该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔，第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层，形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

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