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1. 发明授权

US06274440B1 Manufacturing of cavity fuses on gate conductor level 失效
标题翻译：在栅极导体级制造腔体保险丝
公开(公告)号：US06274440B1
公开(公告)日：2001-08-14
申请号：US09282134
申请日：1999-03-31
申请人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
发明人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
摘要翻译：用于在栅极导体堆叠上形成腔体熔断器的结构和方法。该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔，第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层，形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

2. 发明授权

US5939335A Method for reducing stress in the metallization of an integrated circuit 失效
标题翻译：降低集成电路金属化应力的方法
公开(公告)号：US5939335A
公开(公告)日：1999-08-17
申请号：US3107
申请日：1998-01-06
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/336
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

3. 发明授权

US06208008B1 Integrated circuits having reduced stress in metallization 失效
标题翻译：集成电路在金属化中具有降低的应力
公开(公告)号：US06208008B1
公开(公告)日：2001-03-27
申请号：US09260702
申请日：1999-03-02
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L2941
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

4. 发明授权

US06566238B2 Metal wire fuse structure with cavity 有权
标题翻译：金属线熔丝结构带腔
公开(公告)号：US06566238B2
公开(公告)日：2003-05-20
申请号：US09860570
申请日：2001-05-21
申请人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
发明人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2144
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译：集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。

5. 发明授权

US06268638B1 Metal wire fuse structure with cavity 失效
标题翻译：金属线熔丝结构带腔
公开(公告)号：US06268638B1
公开(公告)日：2001-07-31
申请号：US09258563
申请日：1999-02-26
申请人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
发明人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2702
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译：集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。

6. 发明授权

US06486526B1 Crack stop between neighboring fuses for protection from fuse blow damage 有权
标题翻译：相邻保险丝之间的断裂停止保护熔断器损坏
公开(公告)号：US06486526B1
公开(公告)日：2002-11-26
申请号：US09223826
申请日：1999-01-04
申请人： Chandrasekhar Narayan , Edward W. Kiewra , Carl J. Radens , Axel C. Brintzinger
发明人： Chandrasekhar Narayan , Edward W. Kiewra , Carl J. Radens , Axel C. Brintzinger
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.
摘要翻译：描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底整体的保险丝组; 并且散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。在保险丝熔断操作期间，由激光束击中的点周围的空隙作为裂纹停止，以防止对存在的相邻电路元件或其它熔断体的损坏。通过适当地定形和定位空隙，可以获得保险丝之间更紧密的间距。

7. 发明授权

US6037648A Semiconductor structure including a conductive fuse and process for fabrication thereof 失效
标题翻译：包括导电熔丝的半导体结构及其制造方法
公开(公告)号：US6037648A
公开(公告)日：2000-03-14
申请号：US105647
申请日：1998-06-26
申请人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
发明人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L29/00
CPC分类号： H01L21/76885 , H01L23/5256 , H01L2924/0002
摘要： A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.
摘要翻译：包括半导体衬底的半导体结构，衬底上的导电电平和位于导电水平处的金属熔断器，其中熔丝包括其上的自对准电介质蚀刻停止层以及其制造工艺。

8. 发明申请

US20110109998A1 RECORDING HEAD WITH TILTED ORIENTATION 有权
标题翻译：记录头与倾斜方向
公开(公告)号：US20110109998A1
公开(公告)日：2011-05-12
申请号：US12614275
申请日：2009-11-06
申请人： David Berman , Robert G. Biskeborn , Michel Despont , Philipp Herget , Wayne Isami Imaino , Pierre-Olivier Jubert , Peter V. Koeppe , Chandrasekhar Narayan
发明人： David Berman , Robert G. Biskeborn , Michel Despont , Philipp Herget , Wayne Isami Imaino , Pierre-Olivier Jubert , Peter V. Koeppe , Chandrasekhar Narayan
IPC分类号： G11B5/33 , B05D5/12
CPC分类号： G11B5/3163 , G11B5/00826 , G11B5/398
摘要： In one embodiment, a read sensor for a recording head for a magnetic media storage system, has first and second shields, and a magneto-resistive sensor disposed between and shielded by the first and second shields in which the sensing axis of the sensor is tilted with respect to the recording surface of the head. In one embodiment, the sensing axis is oriented at an angle between 10 and 60 degrees with respect to the normal of the recording surface. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，用于磁性介质存储系统的记录头的读取传感器具有第一和第二屏蔽以及设置在第一和第二屏蔽之间并被传感器的感测轴倾斜的屏蔽的磁阻传感器相对于头部的记录表面。在一个实施例中，感测轴相对于记录表面的法线定向成10度至60度的角度。描述和要求保护其他实施例。

9. 发明授权

US07486845B2 Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter 有权
标题翻译：波导偏振分束器及制造波导线栅偏振光束分离器的方法
公开(公告)号：US07486845B2
公开(公告)日：2009-02-03
申请号：US11870463
申请日：2007-10-11
申请人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
发明人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
IPC分类号： G02B6/00 , G02B6/10
CPC分类号： G02B6/126 , B29D11/00759 , G02B6/136 , G02B2006/1215
摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.
摘要翻译：实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点，这将导致轻微的过度损失。在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

10. 发明申请

US20050121711A1 Chip and wafer integration process using vertical connections 有权
公开(公告)号：US20050121711A1
公开(公告)日：2005-06-09
申请号：US11033926
申请日：2005-01-12
申请人： H. Pogge , Roy Yu , Chandrika Prasad , Chandrasekhar Narayan
发明人： H. Pogge , Roy Yu , Chandrika Prasad , Chandrasekhar Narayan
IPC分类号： H01L23/12 , H01L21/68 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/525 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/8234 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L24/10 , H01L21/6835 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L24/13 , H01L24/81 , H01L25/0652 , H01L2224/03002 , H01L2224/0401 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/0557 , H01L2224/05572 , H01L2224/05644 , H01L2224/06181 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/17181 , H01L2224/81005 , H01L2224/94 , H01L2924/01004 , H01L2924/01006 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2224/11 , H01L2224/03 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

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