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    • 2. 发明授权
    • Catalytic reactor
    • 催化反应器
    • US06197267B1
    • 2001-03-06
    • US08900405
    • 1997-07-25
    • Munir-ud-Din Naeem
    • Munir-ud-Din Naeem
    • F01N328
    • B01D53/885B01D53/32B01D53/8668B01J19/088B01J19/249B01J2219/0809B01J2219/0835B01J2219/0841B01J2219/0845B01J2219/0849B01J2219/0883F01N3/0892
    • A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.
    • 用于挥发性有机化合物(VOC)的电晕破坏的反应器,用于反应器的多表面催化剂和制备用于反应器的催化剂的方法。 反应器具有具有增强的表面积的高电介质材料的催化剂。 通过在衬底上沉积高介电层,然后在电介质层上沉积导电层来形成催化剂层堆叠。 催化剂层堆叠被低RF能量离子轰击以形成增强的表面积并在导电层上形成保护层。 催化剂层堆叠可以连接回来形成双面催化剂层堆叠。 可以将催化剂层堆叠切成小块,在反应器中使用,或者可以使用整个催化剂层堆叠。
    • 3. 发明授权
    • Method of reducing metal voids in semiconductor device interconnection
    • 减少半导体器件互连中的金属空隙的方法
    • US06177337B1
    • 2001-01-23
    • US09003102
    • 1998-01-06
    • Munir-ud-Din Naeem
    • Munir-ud-Din Naeem
    • H01L214763
    • H01L21/32136H01L21/76838
    • The occurrence of defects in interconnect metal structure is reduced or eliminated by a method wherein a semiconductor substrate having a dielectric layer, a metal-containing electrically conductive layer and a patterned photoresist layer, the metal-containing electrically conductive layer overlying the dielectric layer and the photoresist layer overlying the conductive layer such that portions of the conductive layer are exposed, is treated using a sequence of at least four reactive ion etching environments, each having a different etchant composition from the previous and/or subsequent environment. The invention is especially applicable for metal interconnect structures having aluminum and/or copper as the primary conductive layer.
    • 通过以下方法减少或消除互连金属结构中的缺陷的发生:其中具有介电层,含金属的导电层和图案化的光致抗蚀剂层的半导体衬底,覆盖在电介质层上的含金属的导电层和 使用覆盖导电层的光致抗蚀剂层,使得导电层的部分暴露,使用至少四个反应离子蚀刻环境的序列来处理,每个反应离子蚀刻环境具有与先前和/或后续环境不同的蚀刻剂组成。 本发明特别适用于具有铝和/或铜作为主导电层的金属互连结构。
    • 4. 发明授权
    • High selectivity collar oxide etch processes
    • 高选择性环氧化物蚀刻工艺
    • US6066566A
    • 2000-05-23
    • US14805
    • 1998-01-28
    • Munir-ud-Din NaeemMatthew J. SendelbachTing-Hao Wang
    • Munir-ud-Din NaeemMatthew J. SendelbachTing-Hao Wang
    • H01L21/302H01L21/3065H01L21/334H01L21/8242H01L27/108H01L21/00
    • H01L27/10861H01L29/66181
    • A collar oxide is formed in a provided a semiconductor substrate having (3) a partially full trench, (2) (i) fill surface defined by fill material partially filling said trench, (ii) upper surface outside of said trench, and (iii) trench sidewall surface not covered by said fill material, and (3) a conformal oxide layer overlying said fill, upper, and sidewall surfaces, by selectively etching as follows:(a) contacting the substrate with a mixture of hydrogen-containing fluorocarbon and an oxygen source under reactive ion etching conditions until at least a portion of the conformal oxide layer on the upper surface is removed, and(b) contacting the substrate from step (a) with a mixture of a hydrogen-free fluorocarbon and a diluent gas under reactive ion etching conditions to further remove conformal oxide remaining on the fill surface and to overetch the upper and fill surfaces, whereby a substantial portion of conformal oxide remains on the side walls to form the collar oxide.A further step (c) may be added after the overetching to remove any residual byproduct polymer deposits. The methods are especially adapted for use in the manufacture of high aspect ratio trench capacitors for integrated circuits. The method provides reduced degradation of pad nitride layers and may be conducted without the use of CO gas.
    • 在所提供的半导体衬底中形成环状氧化物,其具有(3)部分全沟槽,(2)(i)由部分填充所述沟槽的填充材料限定的填充表面,(ii)所述沟槽外部的上表面,和(iii) )沟槽侧壁表面,以及(3)通过如下选择性蚀刻来覆盖所述填充物,上侧壁和侧壁表面的共形氧化物层:(a)使基底与含氢碳氟化合物的混合物和 在反应离子蚀刻条件下的氧源,直到去除上表面上的共形氧化物层的至少一部分,和(b)使来自步骤(a)的基底与无氢氟碳化合物和稀释气体的混合物 在反应离子蚀刻条件下,以进一步除去残留在填充表面上的保形氧化物,并且去除上表面和填充表面,由此大部分共形氧化物残留在侧壁上以形成环氧化物。 在过蚀刻之后可以加入另外的步骤(c)以除去任何残留的副产物聚合物沉积物。 该方法特别适用于制造用于集成电路的高宽比沟槽电容器。 该方法提供了氮化物层的降低的降低,并且可以在不使用CO气体的情况下进行。
    • 5. 发明授权
    • Method of making dielectric catalyst structures
    • 制造电介质催化剂结构的方法
    • US06193832B1
    • 2001-02-27
    • US08900406
    • 1997-07-25
    • Munir-ud-Din Naeem
    • Munir-ud-Din Naeem
    • B32B3112
    • B01J35/0033B01J37/0244H05H1/2406H05H2001/2412H05H2245/121Y10T156/1052
    • A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.
    • 用于挥发性有机化合物(VOC)的电晕破坏的反应器,用于反应器的多表面催化剂和制备用于反应器的催化剂的方法。 反应器具有具有增强的表面积的高电介质材料的催化剂。 通过在衬底上沉积高介电层,然后在电介质层上沉积导电层来形成催化剂层堆叠。 催化剂层堆叠被低RF能量离子轰击以形成增强的表面积并在导电层上形成保护层。 催化剂层堆叠可以连接回来形成双面催化剂层堆叠。 可以将催化剂层堆叠切成小块,在反应器中使用,或者可以使用整个催化剂层堆叠。
    • 6. 发明授权
    • Reducing metal voids during BEOL metallization
    • 在BEOL金属化期间减少金属空隙
    • US06177286B1
    • 2001-01-23
    • US09159952
    • 1998-09-24
    • Dureseti ChidambarraoMunir-ud-Din Naeem
    • Dureseti ChidambarraoMunir-ud-Din Naeem
    • H01L2166
    • H01L21/76802H01L21/31116H01L21/76801H01L21/76834
    • A process for making metal lines in BEOL semiconductor devices. The process reduces metal voids in the metal lines. In one embodiment, metal lines, including a top barrier blanket are formed over an interlevel dielectric. An insulating layer having tensile stress is formed over the metal lines. A first compressive oxide layer is formed over the insulating layer, wherein the insulating layer provides a tensile stress on the metal lines and the compressive oxide layer provides a compressive stress on the metal lines resulting in reduction of metal voids. The compressive oxide layer is etched with a first type of gas until the insulating layer is reached. The insulating layer is etched with addition of gases to facilitate end-point detection. This second type of gas is monitored for an emission of species at an intensity level having a specific wavelength optical emission, and the etching is stopped when the intensity level is reached.
    • 在BEOL半导体器件中制作金属线的工艺。 该过程减少金属线中的金属空隙。 在一个实施例中,包括顶部阻挡层的金属线形成在层间电介质上。 在金属线上形成具有拉伸应力的绝缘层。 第一压缩氧化物层形成在绝缘层上,其中绝缘层在金属线上提供拉伸应力,并且压缩氧化物层在金属线上提供压缩应力,从而减少金属空隙。 用第一种类型的气体蚀刻压缩氧化物层,直到达到绝缘层。 通过添加气体来蚀刻绝缘层以促进端点检测。 对具有特定波长光发射的强度级别的物质的发射进行第二种类型的气体监测,并且当达到强度水平时停止蚀刻。