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1. 发明授权

US5590345A Advanced parallel array processor(APAP) 失效
标题翻译：高级并行阵列处理器（APAP）
公开(公告)号：US5590345A
公开(公告)日：1996-12-31
申请号：US887630
申请日：1992-05-22
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F15/8092 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/3834 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , F02B2075/027
摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
摘要翻译：一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

2. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

3. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

4. 发明申请

US20140082272A1 Memory Reorder Queue Biasing Preceding High Latency Operations 有权
标题翻译：内存重新排序队列偏差前置高延迟操作
公开(公告)号：US20140082272A1
公开(公告)日：2014-03-20
申请号：US13781519
申请日：2013-02-28
申请人： Mark A. Brittain , John S. Dodson , Stephen Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G11C11/406 , G06F13/16
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的方法。该方法包括确定第一存储器等级的延迟存储器刷新操作的计数。响应于接近高优先级阈值的计数，发出用于第一存储器级的早期高优先级刷新通知，其指示在第一存储器级执行高优先级存储器刷新操作的预定时间。响应于早期高优先级刷新通知，动态地修改读取重新排序队列的行为，以便对至少一个针对第一存储器等级的读取命令给出优先级调度，并且在所述至少一个读取命令中执行一个或多个读取命令根据优先级调度的第一内存等级。优先级调度在刷新操作以第一存储器等级开始之前从重新排序队列中移除这些命令。

5. 发明授权

US08650437B2 Computer system and method of protection for the system's marking store 失效
标题翻译：计算机系统和系统标记存储的保护方法
公开(公告)号：US08650437B2
公开(公告)日：2014-02-11
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

6. 发明申请

US20110029807A1 IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS 有权
标题翻译：使用存储器SCRUB操作实现增强的存储器可靠性
公开(公告)号：US20110029807A1
公开(公告)日：2011-02-03
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G11C29/08 , G06F11/14 , G06F11/26
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

7. 发明申请

US20090327615A1 Access Speculation Predictor with Predictions Based on a Scope Predictor 失效
标题翻译：基于范围预测器的预测的访问投机预测器
公开(公告)号：US20090327615A1
公开(公告)日：2009-12-31
申请号：US12105360
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译：访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和范围预测器。可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为必要。

8. 发明申请

US20090216985A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING 有权
标题翻译：用于动态选择记忆镜的方法，系统和计算机程序产品
公开(公告)号：US20090216985A1
公开(公告)日：2009-08-27
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

9. 发明授权

US08909874B2 Memory reorder queue biasing preceding high latency operations 有权
标题翻译：在高延迟操作之前，内存重新排序队列偏移
公开(公告)号：US08909874B2
公开(公告)日：2014-12-09
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

10. 发明申请

US20130151578A1 Performing Arithmetic Operations Using Both Large and Small Floating Point Values 有权
公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/483 , G06F5/01
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

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