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1. 发明申请

US20110320911A1 Computer System and Method of Protection for the System's Marking Store 失效
标题翻译：计算机系统和系统标记商店的保护方法
公开(公告)号：US20110320911A1
公开(公告)日：2011-12-29
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： H03M13/09
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

2. 发明授权

US08650437B2 Computer system and method of protection for the system's marking store 失效
标题翻译：计算机系统和系统标记存储的保护方法
公开(公告)号：US08650437B2
公开(公告)日：2014-02-11
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

3. 发明申请

US20110029807A1 IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS 有权
标题翻译：使用存储器SCRUB操作实现增强的存储器可靠性
公开(公告)号：US20110029807A1
公开(公告)日：2011-02-03
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G11C29/08 , G06F11/14 , G06F11/26
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

4. 发明授权

US08103900B2 Implementing enhanced memory reliability using memory scrub operations 有权
标题翻译：使用内存清理操作实现增强的内存可靠性
公开(公告)号：US08103900B2
公开(公告)日：2012-01-24
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

5. 发明授权

US5506957A Synchronization for out of order floating point data loads 失效
标题翻译：无序浮点数据加载同步
公开(公告)号：US5506957A
公开(公告)日：1996-04-09
申请号：US497639
申请日：1995-06-30
申请人： Richard E. Fry , Troy N. Hicks , Larry E. Thatcher
发明人： Richard E. Fry , Troy N. Hicks , Larry E. Thatcher
IPC分类号： G06F9/46 , G06F9/38 , G06F11/00
CPC分类号： G06F9/3824
摘要： A system that allows the continuous accessing of data on a floating point processor unit (FPU), by providing two data ports and corresponding buses between the data cache and the FPU. Further, synchronization between the fixed point unit (FXU), which provides the addresses, and the FPU is provided so that data can be loaded in the event of a data cache miss. This synchronization allows data to be transferred from the DCU to the FPU independent of an error condition (cache miss) on one of the buses. If a cache miss occurs that affects a first one of the buses, then the instruction corresponding to this data is held. Subsequent floating point data is received by the FPU on the second bus not subject to the miss. Synchronization signals include, load ready (LD1.sub.-- RDY) indicating to the FPU that data is on the bus and ready to be moved to the FPU and load not ready (LD1.sub.-- NRDY) that means a floating point load has executed successfully in the FXU, but due to a cache miss, the data is not yet available to the FPU. The FXU sends an address, along an address bus corresponding to the data bus not affected by the miss, for data in the cache. Thus, even in the case of a data cache miss, the FPU can continue operations by loading data, that has been addressed to the data port which does not correspond to the cache miss.
摘要翻译：通过在数据高速缓存和FPU之间提供两个数据端口和相应的总线，允许在浮点处理器单元（FPU）上连续访问数据的系统。此外，提供提供地址的固定点单元（FXU）与FPU之间的同步，使得在数据高速缓存未命中的情况下可以加载数据。该同步允许数据从一个总线上独立于错误状态（高速缓存未命中）从DCU传送到FPU。如果发生影响第一个总线的高速缓存未命中，则保持与该数据相对应的指令。随后的浮点数据由FPU在第二总线上接收，不会丢失。同步信号包括向FPU指示数据在总线上的准备就绪（LD1-RDY），并准备移动到FPU并加载未就绪（LD1-NRDY），这意味着在FXU中成功执行了浮点加载，但是由于缓存未命中，FPU尚未提供数据。对于数据在缓存中，FXU发送地址，沿地址总线对应于不受漏洞影响的数据总线。因此，即使在数据高速缓存未命中的情况下，FPU可以通过加载已经被寻址到不对应于高速缓存未命中的数据端口的数据来继续操作。

6. 发明授权

US5363495A Data processing system with multiple execution units capable of executing instructions out of sequence 失效
标题翻译：具有多个执行单元的数据处理系统能够执行顺序的指令
公开(公告)号：US5363495A
公开(公告)日：1994-11-08
申请号：US750132
申请日：1991-08-26
申请人： Richard E. Fry , Troy N. Hicks
发明人： Richard E. Fry , Troy N. Hicks
IPC分类号： G06F9/38 , G06F9/52 , G06F15/16 , G06F15/177 , G06F15/80
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3885
摘要： A data processing system is provided that includes a plurality of execution units each including independent circuits for storing and executing instructions. A circuit is also included for providing instructions from a sequence of instructions to the execution units where each instruction is provided to only one of the execution units. The system includes a circuit for detecting when an instruction in a first execution unit must complete execution prior to execution of an instruction in a second execution unit to produce correct results. A circuit is further included, responsive to the circuit for detecting, for delaying executing the instruction in the second execution unit until the instruction in the first execution unit has completed execution.
摘要翻译：提供了一种数据处理系统，其包括多个执行单元，每个执行单元包括用于存储和执行指令的独立电路。还包括电路，用于将指令序列提供给执行单元，其中每个指令仅提供给执行单元中的一个。该系统包括用于检测第一执行单元中的指令何时必须在第二执行单元中执行指令之前完成执行以产生正确结果的电路。响应于用于检测的电路，进一步包括用于延迟在第二执行单元中执行指令直到第一执行单元中的指令已经完成执行的电路。

7. 发明授权

US5651188A Lint storage system 失效
标题翻译： Lint存储系统
公开(公告)号：US5651188A
公开(公告)日：1997-07-29
申请号：US700918
申请日：1996-08-21
申请人： Edward T. Swanson , Patrick J. Clark , James J. Visin , Eric R. Kissell , Richard E. Fry
发明人： Edward T. Swanson , Patrick J. Clark , James J. Visin , Eric R. Kissell , Richard E. Fry
IPC分类号： D06F58/22 , F26B19/00
CPC分类号： D06F58/22
摘要： A bulk lint storage system supported by a top panel of a dryer. The storage system includes a elongated lint tray connected to the top panel and having an inlet port at one end for receiving lint laden air and an outlet port. A lid is hingedly connected to the lint tray and can be positioned in an open or closed position. A lint basket having an inlet opening and a plurality of screened outlet openings is slidingly supported on support rails extending from the lid. When the lid is closed the inlet opening of the lint basket aligns with the inlet port of the lint tray wherein lint laden air is supplied into the lint basket. When the lid is positioned in an open position, the lint basket is slidingly removable from the support rails such that accumulated lint may be cleaned therefrom.
摘要翻译：由干燥机的顶部面板支撑的散装棉绒存储系统。存储系统包括连接到顶板的细长的棉绒托盘，并且在一端具有入口端口，用于接收棉绒负载空气和出口。盖子铰接地连接到棉绒托盘并且可以被定位在打开或关闭的位置。具有入口开口和多个筛选的出口开口的棉绒篮被滑动地支撑在从盖延伸的支撑轨道上。当盖子关闭时，棉绒篮子的入口开口与棉绒托盘的入口端口对齐，其中棉绒空气被供应到棉绒篮子中。当盖子处于打开位置时，棉绒篮可以从支撑轨道滑动地移除，从而可以清除积累的绒毛。

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