专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

2. 发明授权

US5590345A Advanced parallel array processor(APAP) 失效
标题翻译：高级并行阵列处理器（APAP）
公开(公告)号：US5590345A
公开(公告)日：1996-12-31
申请号：US887630
申请日：1992-05-22
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F15/8092 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/3834 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , F02B2075/027
摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
摘要翻译：一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

3. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

4. 发明授权

US08909874B2 Memory reorder queue biasing preceding high latency operations 有权
标题翻译：在高延迟操作之前，内存重新排序队列偏移
公开(公告)号：US08909874B2
公开(公告)日：2014-12-09
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

5. 发明申请

US20130151578A1 Performing Arithmetic Operations Using Both Large and Small Floating Point Values 有权
公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/483 , G06F5/01
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

6. 发明授权

US08127106B2 Access speculation predictor with predictions based on a domain indicator of a cache line 有权
标题翻译：使用基于缓存行的域指示符的预测来访问推测预测器
公开(公告)号：US08127106B2
公开(公告)日：2012-02-28
申请号：US12105464
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.
摘要翻译：接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，从第一数据请求中提取第一地址和域指示符。第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态在与所选FSM相关联的寄存器中。

7. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

8. 发明授权

US07793143B2 Switching a defective signal line with a spare signal line without shutting down the computer system 失效
标题翻译：在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线
公开(公告)号：US07793143B2
公开(公告)日：2010-09-07
申请号：US12098294
申请日：2008-04-04
申请人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号相关联的驱动器/接收器对中的开关控制单元线路，以便在从存储器控制器开关控制单元接收到命令时能够用备用线路切换有缺陷的信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

9. 发明申请

US20090327612A1 Access Speculation Predictor with Predictions Based on a Domain Indicator of a Cache Line 有权
标题翻译：基于高速缓存行的域指示器的预测的访问猜测预测器
公开(公告)号：US20090327612A1
公开(公告)日：2009-12-31
申请号：US12105464
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.
摘要翻译：接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，从第一数据请求中提取第一地址和域指示符。第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态在与所选FSM相关联的寄存器中。

10. 发明授权

US07380161B2 Switching a defective signal line with a spare signal line without shutting down the computer system 失效
标题翻译：在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线
公开(公告)号：US07380161B2
公开(公告)日：2008-05-27
申请号：US11056886
申请日：2005-02-11
申请人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式