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1. 发明申请

US20140082272A1 Memory Reorder Queue Biasing Preceding High Latency Operations 有权
标题翻译：内存重新排序队列偏差前置高延迟操作
公开(公告)号：US20140082272A1
公开(公告)日：2014-03-20
申请号：US13781519
申请日：2013-02-28
申请人： Mark A. Brittain , John S. Dodson , Stephen Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G11C11/406 , G06F13/16
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的方法。该方法包括确定第一存储器等级的延迟存储器刷新操作的计数。响应于接近高优先级阈值的计数，发出用于第一存储器级的早期高优先级刷新通知，其指示在第一存储器级执行高优先级存储器刷新操作的预定时间。响应于早期高优先级刷新通知，动态地修改读取重新排序队列的行为，以便对至少一个针对第一存储器等级的读取命令给出优先级调度，并且在所述至少一个读取命令中执行一个或多个读取命令根据优先级调度的第一内存等级。优先级调度在刷新操作以第一存储器等级开始之前从重新排序队列中移除这些命令。

2. 发明授权

US08909874B2 Memory reorder queue biasing preceding high latency operations 有权
标题翻译：在高延迟操作之前，内存重新排序队列偏移
公开(公告)号：US08909874B2
公开(公告)日：2014-12-09
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

3. 发明申请

US20130212330A1 MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS 有权
标题翻译：内存记录器排队高效率运行
公开(公告)号：US20130212330A1
公开(公告)日：2013-08-15
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

4. 发明授权

US09632954B2 Memory queue handling techniques for reducing impact of high-latency memory operations 有权
公开(公告)号：US09632954B2
公开(公告)日：2017-04-25
申请号：US13290702
申请日：2011-11-07
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1626 , G06F13/16
摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

5. 发明申请

US20130117513A1 MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENCY MEMORY OPERATIONS 有权
标题翻译：用于减少高级存储器操作影响的存储器队列处理技术
公开(公告)号：US20130117513A1
公开(公告)日：2013-05-09
申请号：US13290702
申请日：2011-11-07
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/14
CPC分类号： G06F13/1626 , G06F13/16
摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.
摘要翻译：用于处理存储器访问排队的技术防止传递过多的请求，这些请求涉及存储器的区域，这些存储器受到诸如存储器刷新操作，存储器擦除或内部总线校准事件的高等待时间存储器操作到存储器的重新排序队列控制器。存储器控制器包括用于存储未决存储器访问请求的队列，用于接收请求的重新排序队列，以及实现队列控制器的控制逻辑，该队列控制器确定接收到的请求和正在进行的高延迟存储器操作之间是否存在冲突。如果存在冲突，则将请求转发到重新排序队列可能被直接拒绝，或者可能使用与高等待时间操作相冲突的现有排队操作的计数来确定新请求的队列是否将超过阈值此类操作的数量。

6. 发明申请

US20090327615A1 Access Speculation Predictor with Predictions Based on a Scope Predictor 失效
标题翻译：基于范围预测器的预测的访问投机预测器
公开(公告)号：US20090327615A1
公开(公告)日：2009-12-31
申请号：US12105360
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译：访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和范围预测器。可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为必要。

7. 发明授权

US08131974B2 Access speculation predictor implemented via idle command processing resources 失效
标题翻译：通过空闲命令处理资源实现访问推测预测器
公开(公告)号：US08131974B2
公开(公告)日：2012-03-06
申请号：US12105427
申请日：2008-04-18
申请人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/507 , G06F2212/6022 , G06F2212/6024 , Y02D10/13
摘要： An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.
摘要翻译：提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。可以选择其存储区域包括第一地址的FSM。可以从所选择的FSM获得用于存储器区域的历史信息。历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

8. 发明授权

US08122222B2 Access speculation predictor with predictions based on a scope predictor 失效
标题翻译：基于范围预测器访问具有预测的投机预测因子
公开(公告)号：US08122222B2
公开(公告)日：2012-02-21
申请号：US12105360
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译：访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和范围预测器。可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为必要。

9. 发明申请

US20130151578A1 Performing Arithmetic Operations Using Both Large and Small Floating Point Values 有权
公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/483 , G06F5/01
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

10. 发明授权

US08127106B2 Access speculation predictor with predictions based on a domain indicator of a cache line 有权
标题翻译：使用基于缓存行的域指示符的预测来访问推测预测器
公开(公告)号：US08127106B2
公开(公告)日：2012-02-28
申请号：US12105464
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.
摘要翻译：接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，从第一数据请求中提取第一地址和域指示符。第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态在与所选FSM相关联的寄存器中。

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