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1. 发明申请

US20140024181A1 SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US20140024181A1
公开(公告)日：2014-01-23
申请号：US13551054
申请日：2012-07-17
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在PFET部分的RSD上形成非晶硅层。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

2. 发明授权

US08673699B2 Semiconductor structure having NFET extension last implants 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US08673699B2
公开(公告)日：2014-03-18
申请号：US13551054
申请日：2012-07-17
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在PFET部分的RSD上形成非晶硅层。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

3. 发明授权

US08546203B1 Semiconductor structure having NFET extension last implants 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US08546203B1
公开(公告)日：2013-10-01
申请号：US13551100
申请日：2012-07-17
申请人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L29/66628
摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

4. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

5. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

6. 发明授权

US08927387B2 Robust isolation for thin-box ETSOI MOSFETS 有权
标题翻译：薄型ETSOI MOSFET的强大隔离性
公开(公告)号：US08927387B2
公开(公告)日：2015-01-06
申请号：US13442168
申请日：2012-04-09
申请人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
IPC分类号： H01L27/088 , H01L21/336 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76283 , H01L27/1203
摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要翻译：薄型BOX ETSOI器件，具有强大的隔离性和制造方法。该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层，第一半导体晶片上的栅极结构。

7. 发明申请

US20130264641A1 ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS 有权
标题翻译：用于薄盒ETSOI MOSFET的稳定隔离
公开(公告)号：US20130264641A1
公开(公告)日：2013-10-10
申请号：US13442168
申请日：2012-04-09
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Sanjay Mehta , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Sanjay Mehta , Stefan Schmitz
IPC分类号： H01L27/088 , H01L21/762 , H01L21/336
CPC分类号： H01L21/84 , H01L21/76283 , H01L27/1203
摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要翻译：薄型BOX ETSOI器件，具有强大的隔离性和制造方法。该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层，第一半导体晶片上的栅极结构。

8. 发明申请

US20130319613A1 CUT-VERY-LAST DUAL-EPI FLOW 有权
标题翻译：切割 - 最近的双EPI流程
公开(公告)号：US20130319613A1
公开(公告)日：2013-12-05
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/308
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

9. 发明授权

US08592290B1 Cut-very-last dual-EPI flow 有权
标题翻译：切割最后的双EPI流程
公开(公告)号：US08592290B1
公开(公告)日：2013-11-26
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

10. 发明授权

US08569152B1 Cut-very-last dual-epi flow 有权
标题翻译：切割最后的双面流
公开(公告)号：US08569152B1
公开(公告)日：2013-10-29
申请号：US13487413
申请日：2012-06-04
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

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