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1. 发明授权

US08927387B2 Robust isolation for thin-box ETSOI MOSFETS 有权
标题翻译：薄型ETSOI MOSFET的强大隔离性
公开(公告)号：US08927387B2
公开(公告)日：2015-01-06
申请号：US13442168
申请日：2012-04-09
申请人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
IPC分类号： H01L27/088 , H01L21/336 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76283 , H01L27/1203
摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要翻译：薄型BOX ETSOI器件，具有强大的隔离性和制造方法。该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层，第一半导体晶片上的栅极结构。

2. 发明授权

US09034701B2 Semiconductor device with a low-k spacer and method of forming the same 有权
标题翻译：具有低k间隔物的半导体器件及其形成方法
公开(公告)号：US09034701B2
公开(公告)日：2015-05-19
申请号：US13354363
申请日：2012-01-20
申请人： Kangguo Cheng , Bruce B Doris , Ali Khakifirooz , Douglas C La Tulipe
发明人： Kangguo Cheng , Bruce B Doris , Ali Khakifirooz , Douglas C La Tulipe
IPC分类号： H01L21/338 , H01L29/66 , H01L29/772 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78603 , H01L29/0847 , H01L29/4908 , H01L29/495 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/772 , H01L29/785 , H01L29/78654
摘要： A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.
摘要翻译：一种器件包括半导体衬底。半导体衬底上的栅极叠层包括栅极介电层和栅极导体层。低k间隔物与栅介质层相邻。升高的源极/漏极（RSD）区域与低k间隔物相邻。低k间隔物嵌入在RSD区域上的ILD中。

3. 发明授权

US07847358B2 High performance strained CMOS devices 有权
标题翻译：高性能应变CMOS器件
公开(公告)号：US07847358B2
公开(公告)日：2010-12-07
申请号：US11462648
申请日：2006-08-04
申请人： Bruce B Doris , Oleg G Gluschenkov
发明人： Bruce B Doris , Oleg G Gluschenkov
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/78 , H01L29/7846
摘要： A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate. The at least one overhang is selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow. For the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, and for the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.
摘要翻译：形成在基板上的半导体结构和用于防止基板的确定部分中的氧化诱发应力的工艺。该结构包括n-FET器件和p-FET器件，并且具有至少一个突出端的浅沟槽隔离被选择性地配置为防止在衬底的确定部分中的氧化诱导应力。所述至少一个突出部被选择性地构造成防止在与电流的方向平行的方向和横向于电流的方向的方向中的至少一个中的氧化诱发应力。对于n-FET器件，至少一个突出端选择性地布置在电流流动的方向上并且横向于电流，并且对于p-FET器件，至少一个突出端横向于电流流动布置以防止性能下降压应力。

4. 发明授权

US07122849B2 Stressed semiconductor device structures having granular semiconductor material 失效
公开(公告)号：US07122849B2
公开(公告)日：2006-10-17
申请号：US10707018
申请日：2003-11-14
申请人： Bruce B Doris , Michael P Belyansky , Diane C Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B Doris , Michael P Belyansky , Diane C Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

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