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1. 发明申请

US20090162988A1 METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR 有权
公开(公告)号：US20090162988A1
公开(公告)日：2009-06-25
申请号：US12395076
申请日：2009-02-27
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
IPC分类号： H01L21/77 , H01L21/762
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

2. 发明授权

US08039359B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US08039359B2
公开(公告)日：2011-10-18
申请号：US12395076
申请日：2009-02-27
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L21/76 , H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

3. 发明授权

US07538395B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US07538395B2
公开(公告)日：2009-05-26
申请号：US11859570
申请日：2007-09-21
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L23/62 , G11C11/36 , H01L21/00
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

4. 发明申请

US20090079022A1 METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR 有权
标题翻译：形成低电容ESD器件及其结构的方法
公开(公告)号：US20090079022A1
公开(公告)日：2009-03-26
申请号：US11859570
申请日：2007-09-21
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
IPC分类号： H01L29/866 , H01L21/329
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

5. 发明申请

US20080258210A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20080258210A1
公开(公告)日：2008-10-23
申请号：US11737923
申请日：2007-04-20
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

6. 发明授权

US08035161B2 Semiconductor component 有权
标题翻译：半导体元件
公开(公告)号：US08035161B2
公开(公告)日：2011-10-11
申请号：US12790987
申请日：2010-06-01
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

7. 发明授权

US07767529B2 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US07767529B2
公开(公告)日：2010-08-03
申请号：US11737923
申请日：2007-04-20
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

8. 发明申请

US20100237409A1 SEMICONDUCTOR COMPONENT 有权
标题翻译：半导体元件
公开(公告)号：US20100237409A1
公开(公告)日：2010-09-23
申请号：US12790987
申请日：2010-06-01
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

9. 发明申请

US20060039217A1 Power efficient read circuit for a serial output memory device and method 有权
标题翻译：用于串行输出存储器件和方法的高效读取电路
公开(公告)号：US20060039217A1
公开(公告)日：2006-02-23
申请号：US10921754
申请日：2004-08-17
申请人： Neal Berger , George Chang , Pearl Cheng , Anne Koh
发明人： Neal Berger , George Chang , Pearl Cheng , Anne Koh
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1027 , G11C7/103
摘要： An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j
摘要翻译：集成电路存储器件具有以多个阵列排列的多个存储单元。每个阵列具有多个行，多个列线以及连接到每个阵列中的存储器单元的多条行线。阵列中的存储单元可由列线和行行寻址。列地址解码器接收列地址信号并且响应地选择每个阵列的一个或多个列线。行地址解码器接收行地址信号并且响应地选择每个阵列的行线。存储器件还具有多个（k）个读出放大器，其中一个读出放大器与每个阵列相关联，可连接到阵列的一个或多个列线，并接收从寻址的存储器单元提供的信号。存储器件还具有寄存器; 和控制电路。控制电路接收读取命令，并且时钟信号，并且响应于读取命令，激活多个（k）个读出放大器（k）中的第一个（j）一段足以感测信号的时间段在与多个（j）个读出放大器中的每一个相关联的连接列线上。控制电路将信号锁存到寄存器中; 并且去激活所述第一多个（j）读出放大器; 并响应于时钟信号串行输出来自寄存器的信号。

10. 发明授权

US5968950A Apo B-secretion/MTP inhibitor hydrochloride salt 失效
标题翻译： Apo B分泌/ MTP抑制剂盐酸盐
公开(公告)号：US5968950A
公开(公告)日：1999-10-19
申请号：US33506
申请日：1998-03-02
申请人： George J. Quallich , George Chang , Lewin T. Wint
发明人： George J. Quallich , George Chang , Lewin T. Wint
IPC分类号： A61K31/47 , A61K31/472 , A61P1/00 , A61P3/04 , A61P3/06 , A61P3/08 , A61P3/10 , A61P9/10 , A61P43/00 , C07D217/02 , C07D217/04 , A01N43/42
CPC分类号： C07D217/02 , C07D217/04
摘要： A hydrochloride salt of an Apo B secretion/MTP inhibitor, methods of making the salt, methods of using the salt and pharmaceutical compositions containing the salt are disclosed.
摘要翻译：公开了Apo B分泌物/ MTP抑制剂的盐酸盐，盐的制备方法，盐的使用方法和含有该盐的药物组合物。

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