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1. 发明授权

US06902624B2 Massively parallel atomic layer deposition/chemical vapor deposition system 有权
公开(公告)号：US06902624B2
公开(公告)日：2005-06-07
申请号：US10282609
申请日：2002-10-29
申请人： Thomas E. Seidel , Adrian Jansz , Jurek Puchacz , Ken Doering
发明人： Thomas E. Seidel , Adrian Jansz , Jurek Puchacz , Ken Doering
IPC分类号： C23C16/44 , C23C16/455 , C23C16/54 , C33C16/00 , C23F1/00 , H01L21/306
CPC分类号： C23C16/45544 , C23C16/4412 , C23C16/45546 , C23C16/54
摘要： A method and apparatus for the use of individual vertically stacked ALD or CVD reactors. Individual reactors are independently operable and maintainable. The gas inlet and output are vertically configured with respect to the reactor chamber for generally axi-symmetric process control. The chamber design is modular in which cover and base plates forming the reactor have improved flow design.

2. 发明授权

US10896823B2 Limited dose atomic layer processes for localizing coatings on non-planar surfaces 有权
公开(公告)号：US10896823B2
公开(公告)日：2021-01-19
申请号：US16665940
申请日：2019-10-28
申请人： Thomas E. Seidel , Michael Current
发明人： Thomas E. Seidel , Michael Current
IPC分类号： H01L21/311 , H01L21/02 , G01T3/00
摘要： Processes for localized film deposition on semiconductor device surfaces having non-planar features. The processes use combinations of Limited-Dose Atomic Layer Etch, Limited Dose Atomic Layer Deposition, and Atomic Layer Deposition to provide localized coatings only near or on the bottom, or only near the center, or only near or on the top and bottom of trench and Fin features.

3. 发明申请

US20100012036A1 ISOLATION FOR MULTI-SINGLE-WAFER PROCESSING APPARATUS 审中-公开
标题翻译：多单波长加工设备的隔离
公开(公告)号：US20100012036A1
公开(公告)日：2010-01-21
申请号：US12502142
申请日：2009-07-13
申请人： Hugo Silva , Martin Dauelsberg , Johannes Lindner , Thomas E. Seidel , Gerhard K. Strauch
发明人： Hugo Silva , Martin Dauelsberg , Johannes Lindner , Thomas E. Seidel , Gerhard K. Strauch
IPC分类号： C23C16/46 , C23C16/00
CPC分类号： C23C16/45544 , C23C16/4409
摘要： An MSW processing apparatus includes two or more semi-isolated reaction chambers separated from one another by isolation regions configured with two or more TIG elements, either or both of which may be independently purged. The TIG elements may be configured in a staircase-like fashion and include vertical and horizontal conductance spacings, sized so that, under different operational process temperatures of the MSW processing apparatus, a change in the horizontal conductance spacing is less than a change in the vertical conductance spacing.
摘要翻译： MSW处理装置包括由两个或多个TIG元件构成的隔离区彼此隔开的两个或更多个半隔离的反应室，其中一个或两个可独立地清除。 TIG元件可以被配置成阶梯式的并且包括垂直和水平的电导间隔，其尺寸使得在MSW处理设备的不同的操作过程温度下，水平电导间隔的变化小于垂直方向的变化电导间距。

4. 发明授权

US06638859B2 Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition 有权
标题翻译：在原子层沉积期间实现连续界面和超薄膜的设备和方法
公开(公告)号：US06638859B2
公开(公告)日：2003-10-28
申请号：US10256899
申请日：2002-09-27
申请人： Ofer Sneh , Thomas E. Seidel , Carl Galewski
发明人： Ofer Sneh , Thomas E. Seidel , Carl Galewski
IPC分类号： H01L2144
CPC分类号： C23C16/0272 , C23C16/02 , C23C16/45536 , C23C16/45544
摘要： A method and apparatus for performing atomic layer deposition in which a surface of a substrate is pretreated to make the surface of the substrate reactive for performing atomic layer deposition.
摘要翻译：一种用于进行原子层沉积的方法和装置，其中预处理衬底的表面以使衬底的表面反应以进行原子层沉积。

5. 发明授权

US6100184A Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer 失效
标题翻译：使用低介电常数材料制造用于层间电介质层的双镶嵌互连结构的方法
公开(公告)号：US6100184A
公开(公告)日：2000-08-08
申请号：US914995
申请日：1997-08-20
申请人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
发明人： Bin Zhao , Prahalad K. Vasudev , Ronald S. Horwath , Thomas E. Seidel , Peter M. Zeitzoff
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7681 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/902
摘要： A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.
摘要翻译：一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。低介电常数（低+ 531）介电材料用于在金属化层之间形成层间电介质层（ILD）层，其中通孔和沟槽开口形成在低+ 531 ILD中。双镶嵌技术允许通孔和沟槽开口同时被填充。

6. 发明授权

US10996562B2 Method and structure for nanoimprint lithography masks using optical film coatings 有权
公开(公告)号：US10996562B2
公开(公告)日：2021-05-04
申请号：US16160479
申请日：2018-10-15
申请人： Thomas E. Seidel
发明人： Thomas E. Seidel
IPC分类号： B29C43/00 , B29C59/00 , B29C59/02 , G03F7/00
摘要： Structures and associated methods for making smaller physical feature sizes for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.

7. 发明授权

US10156786B2 Method and structure for nanoimprint lithography masks using optical film coatings 有权
公开(公告)号：US10156786B2
公开(公告)日：2018-12-18
申请号：US15259769
申请日：2016-09-08
申请人： Thomas E. Seidel
发明人： Thomas E. Seidel
IPC分类号： B29C43/00 , G03F7/00 , B29C59/02 , B29C59/00
摘要： Structures and associated methods for making high index of refraction surface coatings for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.

8. 发明授权

US06897119B1 Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition 有权
标题翻译：在原子层沉积期间实现连续界面和超薄膜的设备和方法
公开(公告)号：US06897119B1
公开(公告)日：2005-05-24
申请号：US10666694
申请日：2003-09-18
申请人： Ofer Sneh , Thomas E. Seidel , Carl Galewski
发明人： Ofer Sneh , Thomas E. Seidel , Carl Galewski
IPC分类号： C23C16/02 , C23C16/44 , C23C16/455 , H01L21/76
CPC分类号： C23C16/45525 , C23C16/02 , C23C16/0272
摘要： A method and apparatus for performing atomic layer deposition in which a surface of a substrate is pretreated to make the surface of the substrate reactive for performing atomic layer deposition.
摘要翻译：一种用于进行原子层沉积的方法和装置，其中预处理衬底的表面以使衬底的表面反应以进行原子层沉积。

9. 发明授权

US5879459A Vertically-stacked process reactor and cluster tool system for atomic layer deposition 失效
标题翻译：用于原子层沉积的垂直堆叠过程反应器和簇工具系统
公开(公告)号：US5879459A
公开(公告)日：1999-03-09
申请号：US920708
申请日：1997-08-29
申请人： Prasad N. Gadgil , Thomas E. Seidel
发明人： Prasad N. Gadgil , Thomas E. Seidel
IPC分类号： C23C16/44 , C23C16/455 , C23C16/54 , C30B25/12 , C30B25/14 , H01L21/205 , C23C16/00
CPC分类号： C23C16/45546 , C23C16/44 , C23C16/54 , C30B25/12 , C30B25/14
摘要： A low profile, compact atomic layer deposition reactor (LP-CAR) has a low-profile body with a substrate processing region adapted to serve a single substrate or a planar array of substrates, and a valved load and unload port for substrate loading and unloading to and from the LP-CAR. The body has an inlet adapted for injecting a gas or vapor at the first end, and an exhaust exit adapted for evacuating gas and vapor at the second end. The LP-CAR has an external height no greater than any horizontal dimension, and more preferably no more than two-thirds any horizontal dimension, facilitating a unique system architecture. An internal processing region is distinguished by having a vertical extent no greater than one fourth the horizontal extent, facilitating fast gas switching. In some embodiments one substrate at a time is processed, and in other embodiments there may be multiple substrates arranged in the processing region in a planar array. The compact reactor is distinguished by individual injectors, each of which comprise a charge tube formed between a charge valve and an injection valve. The charge valve connects the charge tube to a pressure regulated supply, and the injection valve opens the charge tube into the compact reactor. Rapidly cycling the valves injects fixed mass-charges of gas or vapor into the compact reactor. Multiple such compact reactors are stacked vertically, interfaced into a vacuum handling region having a Z-axis robot and a load/unload opening.
摘要翻译：薄型原子层沉积反应器（LP-CAR）具有低轮廓体，其基底处理区域适用于单个基底或平面阵列阵列，以及用于基底装载和卸载的带阀载荷和卸载口往返于LP-CAR。主体具有适于在第一端处喷射气体或蒸气的入口和适于在第二端排出气体和蒸汽的排气出口。 LP-CAR具有不大于任何水平尺寸的外部高度，更优选不超过任何水平尺寸的三分之二，有助于独特的系统架构。内部处理区域的区别在于垂直范围不大于水平范围的四分之一，有利于快速气体切换。在一些实施例中，一次处理一个基板，并且在其他实施例中，可以在平面阵列中布置在处理区域中的多个基板。紧凑型反应器由单独的喷射器区分，每个喷射器包括在充气阀和喷射阀之间形成的进料管。充电阀将充电管连接到压力调节电源，并且注射阀将充电管打开到紧凑型反应堆中。快速循环阀将气体或蒸气的固定质量注入到紧凑型反应堆中。多个这样的紧凑型反应堆被垂直堆叠，接合到具有Z轴机器人和装载/卸载开口的真空处理区域中。

10. 发明授权

US07164203B1 Methods and procedures for engineering of composite conductive by atomic layer deposition 有权
标题翻译：通过原子层沉积工程复合导电的方法和程序
公开(公告)号：US07164203B1
公开(公告)日：2007-01-16
申请号：US11216750
申请日：2005-08-30
申请人： Ana R. Londergan , Thomas E. Seidel
发明人： Ana R. Londergan , Thomas E. Seidel
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76846 , H01L23/5223 , H01L23/53238 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.
摘要翻译：由具有基板界面的基板上的ALD形成由三层构成的复合膜。第一层耦合到衬底界面表面。第一层提供对基底界面表面的粘附和逐层起始的ALD生长。第二层位于第一层和第三层之间，并且在衬底和随后的覆盖膜之间提供导电扩散阻挡层。第三层具有被配置为提供粘合的表面和纹理模板以准备随后的覆盖膜。复合工程的阻挡结构应用于互连，电容和晶体管应用。

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