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1. 发明授权

US07158405B2 Semiconductor memory device having a plurality of memory areas with memory elements 有权
标题翻译：具有多个具有存储元件的存储区域的半导体存储器件
公开(公告)号：US07158405B2
公开(公告)日：2007-01-02
申请号：US10190812
申请日：2002-07-08
申请人： Thomas Böhm , Stefan Lammers , Thomas Röhr
发明人： Thomas Böhm , Stefan Lammers , Thomas Röhr
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C8/12
摘要： A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.
摘要翻译：半导体存储器件具有特别节省空间的存储区域配置，特别是分配给存储区域的选择设备。在操作期间，可以以可控的方式将每个选择装置分配给多个存储区域，使得选择性地每个选择装置可以在分配的存储区域之一中执行寻址和选择。

2. 发明授权

US06473335B2 MRAM configuration 有权
标题翻译： MRAM配置
公开(公告)号：US06473335B2
公开(公告)日：2002-10-29
申请号：US09898222
申请日：2001-07-03
申请人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
发明人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.
摘要翻译：描述了一种磁阻随机存取存储器（MRAM）配置，其中线路驱动器电路分别经由连接节点分配给两个存储单元阵列，结果是驱动器电路的面积实际上可以减半。因此，获得节省空间的架构和更有效的MRAM配置。

3. 发明授权

US06429731B2 CMOS voltage divider 有权
标题翻译： CMOS分压器
公开(公告)号：US06429731B2
公开(公告)日：2002-08-06
申请号：US09816934
申请日：2001-03-23
申请人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
IPC分类号： G05F1595
CPC分类号： G05F3/242
摘要： A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.
摘要翻译：描述了具有包含第一导电类型的串联MOS晶体管的第一链的CMOS分压器。每个MOS晶体管具有相同的几何尺寸，并且同时具有相同的栅源电压。 MOS晶体管在其特性曲线的线性范围内工作，并且在第一链的相对端之间存在待分割的输入电压，并且在每个情况下，其源极端子的电压分数可以被拾取。提供了包含与第一MOS晶体管互补的串联MOS晶体管的第二链。第二链具有与第一MOS晶体管相同数量的晶体管，并且在每种情况下具有相同的几何尺寸。第一链的MOS晶体管以这样的方式连接到第二链的MOS晶体管，使得每个MOS晶体管链为相应的另一个MOS晶体管链产生栅极 - 源极偏置电压。

4. 发明授权

US06545900B2 MRAM module configuration 有权
公开(公告)号：US06545900B2
公开(公告)日：2003-04-08
申请号：US09951242
申请日：2001-09-12
申请人： Thomas Böhm , Dietmar Gogl , Martin Freitag , Stefan Lammers
发明人： Thomas Böhm , Dietmar Gogl , Martin Freitag , Stefan Lammers
IPC分类号： G11C1702
CPC分类号： G11C11/16 , G11C5/025 , H01L27/222
摘要： An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

5. 发明授权

US06618306B2 Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit 有权
标题翻译：具有行和列冗余电路的半导体存储器件及其制造方法
公开(公告)号：US06618306B2
公开(公告)日：2003-09-09
申请号：US10237410
申请日：2002-09-09
申请人： Thomas Böhm , Helmut Kandolf , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Helmut Kandolf , Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C2900
CPC分类号： G11C29/24 , G11C29/46
摘要： A digital circuit configuration includes a memory matrix having M rows and N columns and P
摘要翻译：数字电路配置包括具有M行和N列以及P

6. 发明授权

US06353562B2 Integrated semiconductor memory with redundant units for memory cells 有权
标题翻译：具有用于存储器单元的冗余单元的集成半导体存储器
公开(公告)号：US06353562B2
公开(公告)日：2002-03-05
申请号：US09780326
申请日：2001-02-09
申请人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/787
摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.
摘要翻译：集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。冗余电路用于选择冗余单元。处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。在冗余电路中编写修复信息之前，可以对冗余单元进行测试。所需的电路复杂度相对较低。

7. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

8. 发明授权

US06819142B2 Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption 有权
标题翻译：用于将差分模式信号转换成具有降低待机电流消耗的单端信号的电路
公开(公告)号：US06819142B2
公开(公告)日：2004-11-16
申请号：US10387733
申请日：2003-03-13
申请人： Hans-Heinrich Viehmann , Stefan Lammers
发明人： Hans-Heinrich Viehmann , Stefan Lammers
IPC分类号： H03K1920
CPC分类号： H03K19/018528 , H03K19/0016
摘要： An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.
摘要翻译：一种用于将差分模式信号转换成具有降低的功耗的单端信号的装置。优选实施例包括单端转换器（例如，单端转换器505）和输出晶体管（例如，输出晶体管524），当单端转换器505处于待机状态时，可以将单端转换器505的输出到一个已知的逻辑状态（如高逻辑或低逻辑）。单端缓冲器（反相或非反相）可用于输出信号兼容性转换。

9. 发明申请

US20050157546A1 Precharging the write path of an MRAM device for fast write operation 失效
标题翻译：对MRAM设备的写入路径进行预充电以进行快速写入操作
公开(公告)号：US20050157546A1
公开(公告)日：2005-07-21
申请号：US10758449
申请日：2004-01-15
申请人： Stefan Lammers , Hans-Heinrich Viehmann , Thomas Maffitt , John Barwin
发明人： Stefan Lammers , Hans-Heinrich Viehmann , Thomas Maffitt , John Barwin
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： G11C11/16
摘要： The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.
摘要翻译：在开始磁存储单元的写操作之前，MRAM器件的写入路径被预充电，增加了写操作的速度并减小了写周期时间。参考线是预充电的，可以更好地控制字线和位线写入脉冲，从而缩短上升时间。预充电时间可以隐藏在地址解码时间或冗余评估时间内。本文还描述了用于全局参考电流发生器的电路设计。还公开了一种快速接通电路，其增加对参考线预充电的速度。

10. 发明授权

US06657916B2 Integrated memory with memory cell array 有权
标题翻译：集成存储器与存储单元阵列
公开(公告)号：US06657916B2
公开(公告)日：2003-12-02
申请号：US10054195
申请日：2002-01-22
申请人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
发明人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
IPC分类号： G11C800
CPC分类号： G11C8/00 , G11C8/08
摘要： An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
摘要翻译：集成存储器具有存储单元阵列，其存储单元连接到字线和位线。为了从一个存储单元读取或写入存储单元，第一字线可以通过可控的第一开关器件连接到电源电路，并且第二字线可以经由可控的第二开关器件连接到电源电路。根据第一字线的激活状态，控制电路可以根据第二字线和第二开关器件的激活状态来驱动第一开关器件。因此，当前未使用的现有字线可用于寻址存储单元之一。结果，字线只需要一个接线面。

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