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1. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

2. 发明授权

US06353562B2 Integrated semiconductor memory with redundant units for memory cells 有权
标题翻译：具有用于存储器单元的冗余单元的集成半导体存储器
公开(公告)号：US06353562B2
公开(公告)日：2002-03-05
申请号：US09780326
申请日：2001-02-09
申请人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/787
摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.
摘要翻译：集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。冗余电路用于选择冗余单元。处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。在冗余电路中编写修复信息之前，可以对冗余单元进行测试。所需的电路复杂度相对较低。

3. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

4. 发明授权

US06525974B2 Integrated memory with redundancy 有权
公开(公告)号：US06525974B2
公开(公告)日：2003-02-25
申请号：US09888023
申请日：2001-06-22
申请人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
发明人： Ernst Neuhold , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Böhm , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/846
摘要： An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

5. 发明授权

US06459626B1 Integrated memory having memory cells and reference cells, and corresponding operating method 有权
公开(公告)号：US06459626B1
公开(公告)日：2002-10-01
申请号：US09962703
申请日：2001-09-24
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C7/14 , G11C11/22
摘要： An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

6. 发明授权

US06442100B2 Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US06442100B2
公开(公告)日：2002-08-27
申请号：US09904358
申请日：2001-07-12
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Thomas Röhr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/1048 , G11C11/22
摘要： The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.
摘要翻译：集成存储器具有通过开关元件连接到读写放大器的输入的m≥1位线。每个读或写访问只有一个开关元件被导电连接。存储器设置有影响通过读写放大器和位线发生的读取或写入访问的切换单元。电路单元具有激活输入。列端解码器具有第一解码器级和m个第二解码器级。第二解码器级的输出端连接到每个开关元件的控制输入端。第一解码器级的输出连接到开关单元的启动输入。

7. 发明授权

US06392445B2 Decoder element for producing an output signal having three different potentials 失效
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件
公开(公告)号：US06392445B2
公开(公告)日：2002-05-21
申请号：US09822027
申请日：2001-03-29
申请人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
发明人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
IPC分类号： G11C800
CPC分类号： H03M5/16
摘要： The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.
摘要翻译：解码器元件用于在输出端产生具有三个不同电位的输出信号。第二电势位于第一电位和第三电位之间。解码器元件使得可以基于其连接上的电位在其输出端产生三个电位中的任何一个。

8. 发明授权

US06255855B1 Integrated circuit having a decoder 有权
标题翻译：具有解码器的集成电路
公开(公告)号：US06255855B1
公开(公告)日：2001-07-03
申请号：US09470310
申请日：1999-12-22
申请人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： H03K19084
CPC分类号： G11C8/00 , G11C8/10 , H03K19/084 , H03K19/094 , H03K19/23 , H03M5/16
摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.
摘要翻译：集成电路包括具有输出端和五个输入端的解码器。解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。第二个潜力位于第一个潜力和第三个潜力之间。

9. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

10. 发明授权

US06657916B2 Integrated memory with memory cell array 有权
标题翻译：集成存储器与存储单元阵列
公开(公告)号：US06657916B2
公开(公告)日：2003-12-02
申请号：US10054195
申请日：2002-01-22
申请人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
发明人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
IPC分类号： G11C800
CPC分类号： G11C8/00 , G11C8/08
摘要： An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
摘要翻译：集成存储器具有存储单元阵列，其存储单元连接到字线和位线。为了从一个存储单元读取或写入存储单元，第一字线可以通过可控的第一开关器件连接到电源电路，并且第二字线可以经由可控的第二开关器件连接到电源电路。根据第一字线的激活状态，控制电路可以根据第二字线和第二开关器件的激活状态来驱动第一开关器件。因此，当前未使用的现有字线可用于寻址存储单元之一。结果，字线只需要一个接线面。

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