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1. 发明授权

US06618306B2 Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit 有权
标题翻译：具有行和列冗余电路的半导体存储器件及其制造方法
公开(公告)号：US06618306B2
公开(公告)日：2003-09-09
申请号：US10237410
申请日：2002-09-09
申请人： Thomas Böhm , Helmut Kandolf , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Helmut Kandolf , Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C2900
CPC分类号： G11C29/24 , G11C29/46
摘要： A digital circuit configuration includes a memory matrix having M rows and N columns and P
摘要翻译：数字电路配置包括具有M行和N列以及P

2. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

3. 发明授权

US06429731B2 CMOS voltage divider 有权
标题翻译： CMOS分压器
公开(公告)号：US06429731B2
公开(公告)日：2002-08-06
申请号：US09816934
申请日：2001-03-23
申请人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
IPC分类号： G05F1595
CPC分类号： G05F3/242
摘要： A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.
摘要翻译：描述了具有包含第一导电类型的串联MOS晶体管的第一链的CMOS分压器。每个MOS晶体管具有相同的几何尺寸，并且同时具有相同的栅源电压。 MOS晶体管在其特性曲线的线性范围内工作，并且在第一链的相对端之间存在待分割的输入电压，并且在每个情况下，其源极端子的电压分数可以被拾取。提供了包含与第一MOS晶体管互补的串联MOS晶体管的第二链。第二链具有与第一MOS晶体管相同数量的晶体管，并且在每种情况下具有相同的几何尺寸。第一链的MOS晶体管以这样的方式连接到第二链的MOS晶体管，使得每个MOS晶体管链为相应的另一个MOS晶体管链产生栅极 - 源极偏置电压。

4. 发明授权

US06353562B2 Integrated semiconductor memory with redundant units for memory cells 有权
标题翻译：具有用于存储器单元的冗余单元的集成半导体存储器
公开(公告)号：US06353562B2
公开(公告)日：2002-03-05
申请号：US09780326
申请日：2001-02-09
申请人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/787
摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.
摘要翻译：集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。冗余电路用于选择冗余单元。处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。在冗余电路中编写修复信息之前，可以对冗余单元进行测试。所需的电路复杂度相对较低。

5. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

6. 发明授权

US06496423B2 Chip ID register configuration 有权
标题翻译：芯片ID寄存器配置
公开(公告)号：US06496423B2
公开(公告)日：2002-12-17
申请号：US09898261
申请日：2001-07-03
申请人： Stefan Lammers , Zoltan Manyoki
发明人： Stefan Lammers , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C17/16 , G11C16/20 , H01L2223/5444
摘要： A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.
摘要翻译：芯片ID寄存器配置包括具有各个级的移位寄存器。连接到移位寄存器的保险丝装置具有各自基本上分配给移位寄存器的各个级的各自的熔丝，用于识别具有各种所需和不需要的类别的芯片。熔丝器件存储要通过移位寄存器串行读出的类别的信息以识别芯片。存储单元存储定义信息的项目。逻辑电路根据要识别的芯片的类别，读取所需类别的熔丝器件并读取存储在存储器单元中的非需要类别中的一个定义信息项目。在不占用芯片面积的情况下，可以进行不同芯片的标准测试。

7. 发明授权

US06392445B2 Decoder element for producing an output signal having three different potentials 失效
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件
公开(公告)号：US06392445B2
公开(公告)日：2002-05-21
申请号：US09822027
申请日：2001-03-29
申请人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
发明人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
IPC分类号： G11C800
CPC分类号： H03M5/16
摘要： The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.
摘要翻译：解码器元件用于在输出端产生具有三个不同电位的输出信号。第二电势位于第一电位和第三电位之间。解码器元件使得可以基于其连接上的电位在其输出端产生三个电位中的任何一个。

8. 发明授权

US06259641B1 Integrated memory having sense amplifiers disposed on opposite sides of a cell array 失效
标题翻译：具有设置在单元阵列的相对侧上的读出放大器的集成存储器
公开(公告)号：US06259641B1
公开(公告)日：2001-07-10
申请号：US09560545
申请日：2000-04-28
申请人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/06 , G11C7/1042
摘要： An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.
摘要翻译：集成存储器包括具有存储单元阵列的单元阵列，该存储单元设置在第一位线和第二位线的交点处与单元阵列中的字线。当存储器单元之一被寻址时，如果与每个存储器单元相关联的各个位线处于待机电位，则存储器内容不受影响。包括用于将从存储器单元读取的数据放大到位线的读出放大器，每个与相应的第一和第二位线相关联并且设置在单元阵列的相对侧上。还提供了第一开关元件，每个位线通过该开关元件连接到相关联的读出放大器，以及在其第一开关元件的远离相关读出放大器的该侧上连接每个位线的第二开关元件，到备用电位。列选择线各自连接到第一和第二位线中的至少一个中的第一和第二开关元件的控制连接。每个位线通过第三个开关元件连接到待机电位。第一控制线连接到第一位线中的所有第三开关元件，第二控制线连接到第二位线中的所有第三开关元件。

9. 发明授权

US06255855B1 Integrated circuit having a decoder 有权
标题翻译：具有解码器的集成电路
公开(公告)号：US06255855B1
公开(公告)日：2001-07-03
申请号：US09470310
申请日：1999-12-22
申请人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： H03K19084
CPC分类号： G11C8/00 , G11C8/10 , H03K19/084 , H03K19/094 , H03K19/23 , H03M5/16
摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.
摘要翻译：集成电路包括具有输出端和五个输入端的解码器。解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。第二个潜力位于第一个潜力和第三个潜力之间。

10. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

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