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1. 发明授权

US5283201A High density power device fabrication process 失效
标题翻译：高密度功率器件制造工艺
公开(公告)号：US5283201A
公开(公告)日：1994-02-01
申请号：US927169
申请日：1992-08-07
申请人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
发明人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L21/00 , H01L21/02 , H01L21/265
CPC分类号： H01L21/3065 , H01L21/033 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/41766 , H01L29/42368 , H01L29/511 , H01L29/66545
摘要： A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).
摘要翻译：在包括用于IGBT的P体层（26），N-漏极层（24）和可选的P +层（22）的衬底（20）上形成凹陷栅极功率MOSFET。形成在基板上表面（28）上的开沟保护层（30）被图案化以限定作为条纹或矩阵的暴露区域（46）和保护区域。具有内表面（48）的预定厚度（52）的侧壁间隔件（44）与保护层侧壁接触。第一沟槽（50）形成在具有与侧壁间隔物外表面（47）对准的侧壁并且通过P体层（26）的深度方向延伸至至少预定深度（56）的衬底区域（46）中。栅极氧化物（60）形成在沟槽壁上，栅极多晶硅（62）将沟槽重新填充到衬底上表面（28）附近的水平面（64）。侧壁间隔物（44）之间的氧化物（68）覆盖多晶硅（62）。去除保护层暴露间隔件内表面（48）之间的上基板表面（28'）。该区域被掺杂以在主体层（26'）顶部形成源极层（72），然后被沟槽以形成具有与间隔物内表面对准的侧壁的第二沟槽（80）。第二沟槽（80）限定垂直取向的源极和主体层（86,90），沿着栅极氧化物层（60）堆叠以在第二沟槽（80）的相对侧上形成垂直沟道。

2. 发明授权

US4895810A Iopographic pattern delineated power mosfet with profile tailored recessed source 失效
标题翻译： Iopographic图案描绘功率mosfet与轮廓定制凹槽源
公开(公告)号：US4895810A
公开(公告)日：1990-01-23
申请号：US194874
申请日：1988-05-17
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/033 , H01L21/266 , H01L21/3065 , H01L29/41741 , H01L29/7396 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 --SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

3. 发明授权

US07299158B2 Process control data collection 有权
标题翻译：过程控制数据收集
公开(公告)号：US07299158B2
公开(公告)日：2007-11-20
申请号：US10799851
申请日：2004-03-12
申请人： Nima A. Behkami , Theodore O. Meyer , Thomas C. Hann, Jr.
发明人： Nima A. Behkami , Theodore O. Meyer , Thomas C. Hann, Jr.
IPC分类号： G06F11/00 , G06F7/00
CPC分类号： G06F17/30368 , G05B19/4183 , G05B2219/31282 , G05B2219/45031 , Y02P90/10 , Y10S707/99931
摘要： A data collection system. A data input form receives data, and a message queue receives the data from the data input form, and temporarily manages the data until the data collection system can process the data. A temporary data storage temporarily stores the data received by the message queue while waiting for the data collection system to process the data. A transaction manager receives the data from the message queue and processes the data. A data logger logs the processing transactions of the transaction manager. A data loader receives the data from the transaction manager and prepares the data for storage. A data storage device receives the data from the data loader.
摘要翻译：数据收集系统。数据输入表单接收数据，消息队列从数据输入表单接收数据，并临时管理数据，直到数据收集系统能够处理数据。临时数据存储器在等待数据收集系统处理数据的同时临时存储由消息队列接收的数据。事务管理器从消息队列接收数据并处理数据。数据记录器记录事务管理器的处理事务。数据加载器从事务管理器接收数据并准备数据进行存储。数据存储设备从数据加载器接收数据。

4. 发明授权

US5019522A Method of making topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：使用轮廓定制凹槽源制作地形图案划线功率MOSFET的方法
公开(公告)号：US5019522A
公开(公告)日：1991-05-28
申请号：US460258
申请日：1990-01-02
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L29/41741 , H01L29/7396 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structure, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

5. 发明授权

US5801417A Self-aligned power MOSFET device with recessed gate and source 失效
标题翻译：具有凹入栅极和源极的自对准功率MOSFET器件
公开(公告)号：US5801417A
公开(公告)日：1998-09-01
申请号：US106406
申请日：1993-08-13
申请人： Dah Wen Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
发明人： Dah Wen Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L21/3065 , H01L21/033 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/41766 , H01L29/42368 , H01L29/511 , H01L29/66545
摘要： A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80). Layers (86, 90) have a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers. Source conductor (94) in the second trench contacts the N-source and P-body layers, and an enhanced P+ region at the base of the second trench.
摘要翻译：在包括用于IGBT的P体层（26），N-漏极层（24）和可选的P +层（22）的衬底（20）上形成凹陷栅极功率MOSFET。形成在基板上表面（28）上的开沟保护层（30）被图案化以限定作为条纹或矩阵的暴露区域（46）和保护区域。具有内表面（48）的预定厚度（52）的侧壁间隔件（44）与保护层侧壁接触。第一沟槽（50）形成在具有与侧壁间隔物外表面（47）对准的侧壁并且通过P体层（26）的深度方向延伸至至少预定深度（56）的衬底区域（46）中。栅极氧化物（60）形成在沟槽壁上，栅极多晶硅（62）将沟槽重新填充到衬底上表面（28）附近的水平面（64）。侧壁间隔物（44）之间的氧化物（68）覆盖多晶硅（62）。去除保护层暴露间隔件内表面（48）之间的上基板表面（28'）。该区域被掺杂以在主体层（26'）顶部形成源极层（72），然后被沟槽以形成具有与间隔物内表面对准的侧壁的第二沟槽（80）。第二沟槽（80）限定垂直取向的源极和主体层（86,90），沿着栅极氧化物层（60）堆叠以在第二沟槽（80）的相对侧上形成垂直沟道。层（86,90）具有通过侧壁间隔件的内表面和外表面的预定间隔建立的横向厚度（88）。第二沟槽中的源极导体（94）接触N源极和P-主体层，以及在第二沟槽的基极处的增强的P +区域。

6. 发明授权

US5045903A Topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：地形图案划线功率MOSFET，带轮廓定制凹槽源
公开(公告)号：US5045903A
公开(公告)日：1991-09-03
申请号：US439101
申请日：1989-11-16
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7396 , H01L21/3065 , H01L29/41741 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案限定器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

7. 发明授权

US4483065A Insulated feedthrough expansion seal 失效
标题翻译：绝缘馈通膨胀密封
公开(公告)号：US4483065A
公开(公告)日：1984-11-20
申请号：US445383
申请日：1982-11-29
申请人： Theodore O. Meyer , Gerrit van Ommering
发明人： Theodore O. Meyer , Gerrit van Ommering
IPC分类号： H01B17/30 , H01M2/06 , H01M6/00
CPC分类号： H01B17/30 , H01M2/06 , Y10T29/4911 , Y10T29/49911
摘要： Disclosed is a seal which provides effective hermetic sealing of insulated metallic feedthroughs in metallic containers. The device has particular applicability in the fabrication of pressurized metal/gas battery cells such as those used in spacecraft. A conductive terminus protrudes through a metallic vessel which may be pressurized. It is desired to maintain electrical separation between the terminus and the wall of the vessel by means of a dielectric, which is compressed between the terminus and a metallic boss to provide a hermetic seal. The compressive force is applied radially outwardly by means of drawing a nondeformable pin through a hollow cylindrical barrel constituting the terminus, thereby slightly deforming the barrel and grossly deforming the dielectric. The pin may be either pulled out of the barrel from within the vessel or pushed into the barrel from outside the vessel, but in each case force is applied radially outwardly in a gradual, relatively frictionless fashion. A method for constructing a high pressure battery employing such a seal is described.
摘要翻译：公开了一种在金属容器中提供绝缘金属馈通的有效密封的密封件。该设备在制造加压金属/气体电池单元（例如在航天器中使用的那些）时具有特别的适用性。导电端子突出穿过可以被加压的金属容器。期望通过在终端和金属凸起之间压缩以提供气密密封的电介质来保持容器末端和壁之间的电分离。通过将不可变形的销通过构成终端的中空圆柱形管拉出来，使压缩力径向向外施加，从而使筒的轻微变形并使电介质变形很大。销可以从容器内从桶中拉出或从容器的外部推入桶中，但是在每种情况下，力以逐渐，相对无摩擦的方式径向向外施加。描述了构造使用这种密封件的高压电池的方法。

8. 发明授权

US06797585B1 Nonintrusive wafer marking 有权
标题翻译：非侵入式晶圆标记
公开(公告)号：US06797585B1
公开(公告)日：2004-09-28
申请号：US10680047
申请日：2003-10-07
申请人： Theodore O. Meyer , Nima Behkami
发明人： Theodore O. Meyer , Nima Behkami
IPC分类号： H01L2176
CPC分类号： H01L21/02027 , H01L21/02021 , H01L23/544 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A method for marking a wafer that is cut from a boule. A surface of the boule is marked with an encoded marking that extends completely along a distance of the boule that is used for cutting wafers. The encoded marking is disposed substantially parallel to a length axis of the boule. The wafer is cut from the boule from within the distance, such that the encoded marking along the surface of the boule is disposed at a peripheral edge of the wafer. The encoded marking contains information in regard to the wafer.
摘要翻译：一种用于标记从坯料切割的晶片的方法。该轴的表面标有一个编码的标记，该编码标记完全沿用于切割晶片的轴的距离延伸。编码的标记基本上平行于该轴的长度轴布置。在距离内从晶片切割晶片，使得沿着晶片表面的编码标记设置在晶片的周边边缘。编码的标记包含关于晶片的信息。

9. 发明授权

US06724404B1 Cluster tool reporting system 有权
标题翻译：集群工具报告系统
公开(公告)号：US06724404B1
公开(公告)日：2004-04-20
申请号：US09777996
申请日：2001-02-06
申请人： Thomas C. Hann, Jr. , Mark D. Meyer , Theodore O. Meyer
发明人： Thomas C. Hann, Jr. , Mark D. Meyer , Theodore O. Meyer
IPC分类号： G09G500
CPC分类号： G05B19/4187 , G05B2219/31412 , G05B2219/45031 , Y02P90/205
摘要： A method for determining an up time of a multi-component tool having discrete elements, where the up time determination is based upon different processes that are to be accomplished in the multi-component tool. The discrete elements of the multi-component tool and the different processes to be accomplished in the multi-component tool are identified. Different tool states for the multi-component tool are determined by setting element states for each of the discrete elements of the multi-component tool. A first possible element state indicates that the discrete element is functional, and a second possible element state indicates that the discrete element is nonfunctional. Possible combinations of the element states of the discrete elements are identified as the different tool states of the multi-component tool. A determination is made as to which of the different processes can be accomplished in the different tool states, and a percentage of time usage is determined for the allocation of the multi-component tool to each of the different processes. Rates associated with combinations of the different tool states with the different processes are determined. Process state efficiencies are determined from the rates and the percent of time usage allocated to the processes associated with the rates. A preliminary state efficiency for the different tool states is determined from the process state efficiencies associated with the different tool states. Percent of time conditions are determined for the different tool states, where the percent of time conditions represent ratios of time that the multi-component tool exhibits the associated tool state. The final state efficiencies for the different tool states are determined from the percent of time conditions and the preliminary state efficiencies associated with the different tool states, and the up time is determined from the final state efficiencies.
摘要翻译：一种用于确定具有离散元件的多分量工具的上升时间的方法，其中所述上升时间确定基于将在所述多部件工具中实现的不同过程。识别多组件工具的分立元件以及在多组件工具中要完成的不同过程。通过为多组件工具的每个离散元素设置元素状态来确定多组件工具的不同工具状态。第一个可能的元素状态表示离散元素是有效的，第二个可能的元素状态表示离散元素是非功能的。分离元件的元件状态的可能组合被识别为多组件工具的不同工具状态。确定在不同的工具状态中可以实现哪个不同的过程，并且确定用于将多组件工具分配给每个不同过程的时间使用的百分比。确定与不同工具状态与不同过程的组合相关联的速率。流程状态效率由分配给流程相关流程的时间利用率和百分比确定。根据与不同刀具状态相关联的过程状态效率确定不同刀具状态的初步状态效率。确定不同工具状态的时间条件百分比，其中时间条件的百分比表示多部件工具显示相关工具状态的时间的比率。不同刀具状态的最终状态效率由时间条件的百分比和与不同刀具状态相关联的初始状态效率确定，并且从最终状态效率确定上升时间。

10. 发明授权

US06499001B1 Engineering database feedback system 有权
公开(公告)号：US06499001B1
公开(公告)日：2002-12-24
申请号：US09596909
申请日：2000-06-20
申请人： Theodore O. Meyer
发明人： Theodore O. Meyer
IPC分类号： G06F1900
CPC分类号： G05B19/41865 , G05B2219/31331 , G05B2219/31485 , G05B2219/45031 , Y02P90/20
摘要： A computerized engineering database feedback system provides special processing instructions for processing materials in a production process, and provides historical information related to the materials processed according to the special processing instructions. The system includes a request entry device through which requesting personnel may input special processing information indicating a way to process the materials differently from a normal way of processing of the materials. An instruction processing device receives the special processing information and generates the special-processing instructions based thereon. A process station device receives the special-processing instructions, and presents the special-processing instructions to material-processing personnel. The process station device also provides for inputting material information from the material-processing personnel, where the material information indicates one or more characteristics of the material processed according to the special-processing instructions. The system also includes a relational database in which the special processing information and the material information are compiled and related. An information retrieval device accesses the relational database, searches the relational database for material information related to special processing information, or searches the relational database for special processing information related to material information. Using the system, an engineer who wishes to have a lot of material processed in a special way for an engineering experiment may provide process operators with special-processing instructions. The system also allows the process operators to input information and test data related to the material that is processed according to the special instructions. Further, the system makes the results of the engineering experiment readily available to the company community in the relational database. By accessing the database, company engineers may view the results of previously-conducted experiments, and may thereby avoid wasting company resources by unnecessarily repeating the same experiments.

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