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1. 发明授权

US5019522A Method of making topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：使用轮廓定制凹槽源制作地形图案划线功率MOSFET的方法
公开(公告)号：US5019522A
公开(公告)日：1991-05-28
申请号：US460258
申请日：1990-01-02
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L29/41741 , H01L29/7396 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structure, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

2. 发明授权

US5045903A Topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：地形图案划线功率MOSFET，带轮廓定制凹槽源
公开(公告)号：US5045903A
公开(公告)日：1991-09-03
申请号：US439101
申请日：1989-11-16
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7396 , H01L21/3065 , H01L29/41741 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案限定器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

3. 发明授权

US5283201A High density power device fabrication process 失效
标题翻译：高密度功率器件制造工艺
公开(公告)号：US5283201A
公开(公告)日：1994-02-01
申请号：US927169
申请日：1992-08-07
申请人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
发明人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L21/00 , H01L21/02 , H01L21/265
CPC分类号： H01L21/3065 , H01L21/033 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/41766 , H01L29/42368 , H01L29/511 , H01L29/66545
摘要： A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).
摘要翻译：在包括用于IGBT的P体层（26），N-漏极层（24）和可选的P +层（22）的衬底（20）上形成凹陷栅极功率MOSFET。形成在基板上表面（28）上的开沟保护层（30）被图案化以限定作为条纹或矩阵的暴露区域（46）和保护区域。具有内表面（48）的预定厚度（52）的侧壁间隔件（44）与保护层侧壁接触。第一沟槽（50）形成在具有与侧壁间隔物外表面（47）对准的侧壁并且通过P体层（26）的深度方向延伸至至少预定深度（56）的衬底区域（46）中。栅极氧化物（60）形成在沟槽壁上，栅极多晶硅（62）将沟槽重新填充到衬底上表面（28）附近的水平面（64）。侧壁间隔物（44）之间的氧化物（68）覆盖多晶硅（62）。去除保护层暴露间隔件内表面（48）之间的上基板表面（28'）。该区域被掺杂以在主体层（26'）顶部形成源极层（72），然后被沟槽以形成具有与间隔物内表面对准的侧壁的第二沟槽（80）。第二沟槽（80）限定垂直取向的源极和主体层（86,90），沿着栅极氧化物层（60）堆叠以在第二沟槽（80）的相对侧上形成垂直沟道。

4. 发明授权

US5801417A Self-aligned power MOSFET device with recessed gate and source 失效
标题翻译：具有凹入栅极和源极的自对准功率MOSFET器件
公开(公告)号：US5801417A
公开(公告)日：1998-09-01
申请号：US106406
申请日：1993-08-13
申请人： Dah Wen Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
发明人： Dah Wen Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L21/3065 , H01L21/033 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/41766 , H01L29/42368 , H01L29/511 , H01L29/66545
摘要： A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80). Layers (86, 90) have a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers. Source conductor (94) in the second trench contacts the N-source and P-body layers, and an enhanced P+ region at the base of the second trench.
摘要翻译：在包括用于IGBT的P体层（26），N-漏极层（24）和可选的P +层（22）的衬底（20）上形成凹陷栅极功率MOSFET。形成在基板上表面（28）上的开沟保护层（30）被图案化以限定作为条纹或矩阵的暴露区域（46）和保护区域。具有内表面（48）的预定厚度（52）的侧壁间隔件（44）与保护层侧壁接触。第一沟槽（50）形成在具有与侧壁间隔物外表面（47）对准的侧壁并且通过P体层（26）的深度方向延伸至至少预定深度（56）的衬底区域（46）中。栅极氧化物（60）形成在沟槽壁上，栅极多晶硅（62）将沟槽重新填充到衬底上表面（28）附近的水平面（64）。侧壁间隔物（44）之间的氧化物（68）覆盖多晶硅（62）。去除保护层暴露间隔件内表面（48）之间的上基板表面（28'）。该区域被掺杂以在主体层（26'）顶部形成源极层（72），然后被沟槽以形成具有与间隔物内表面对准的侧壁的第二沟槽（80）。第二沟槽（80）限定垂直取向的源极和主体层（86,90），沿着栅极氧化物层（60）堆叠以在第二沟槽（80）的相对侧上形成垂直沟道。层（86,90）具有通过侧壁间隔件的内表面和外表面的预定间隔建立的横向厚度（88）。第二沟槽中的源极导体（94）接触N源极和P-主体层，以及在第二沟槽的基极处的增强的P +区域。

5. 发明授权

US4895810A Iopographic pattern delineated power mosfet with profile tailored recessed source 失效
标题翻译： Iopographic图案描绘功率mosfet与轮廓定制凹槽源
公开(公告)号：US4895810A
公开(公告)日：1990-01-23
申请号：US194874
申请日：1988-05-17
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/033 , H01L21/266 , H01L21/3065 , H01L29/41741 , H01L29/7396 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 --SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

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