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1. 发明授权

US06684007B2 Optical coupling structures and the fabrication processes 有权
标题翻译：光耦合结构和制造工艺
公开(公告)号：US06684007B2
公开(公告)日：2004-01-27
申请号：US09853449
申请日：2001-05-09
申请人： Tetsuzo Yoshimura , Yasuhito Takahashi , James Roman , Mark Thomas McCormack , Solomon I. Beilin , Wen-chou Vincent Wang , Masaaki Inao
发明人： Tetsuzo Yoshimura , Yasuhito Takahashi , James Roman , Mark Thomas McCormack , Solomon I. Beilin , Wen-chou Vincent Wang , Masaaki Inao
IPC分类号： G02B626
CPC分类号： H01L24/82 , G02B6/06 , G02B6/10 , G02B6/12002 , G02B6/124 , G02B6/13 , G02B6/132 , G02B6/136 , G02B6/26 , G02B6/42 , G02B6/4214 , G02B6/43 , G02B2006/12104 , G02B2006/12107 , G02B2006/12173 , H01L21/6835 , H01L23/48 , H01L23/5389 , H01L24/24 , H01L24/96 , H01L25/167 , H01L2221/68345 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2224/24226 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01056 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/10336 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/18162 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3511 , H05K1/0274 , H05K1/14 , H01L2924/00 , H01L2224/05611 , H01L2924/00014 , H01L2224/05644 , H01L2224/05664
摘要： An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide. The method for making an optical apparatus also comprises inserting at least a portion of an optical device within the aperture so that the optical device is positioned to receive light from the first end of the waveguide.
摘要翻译：一种光学装置，包括具有嵌入式波导的光学基板和适于接收从波导的端部传输的光的光学装置。光学装置包括用于将光学装置耦合到基板的耦合结构。耦合结构具有带孔的薄金属层。光学装置的至少一部分设置在孔中。一种制造光学装置的方法，包括：形成具有嵌入其中的波导的光学基板; 在所述波导的一端上沉积金属层; 以及在所述金属层上沉积聚合物层。通过去除金属层的一部分和设置在波导端部上的聚合物层的一部分，在金属层和聚合物层中形成孔。制造光学装置的方法还包括将光学装置的至少一部分插入孔内，使得光学装置被定位成接收来自波导的第一端的光。

2. 发明授权

US06785447B2 Single and multilayer waveguides and fabrication process 失效
标题翻译：单层和多层波导和制造工艺
公开(公告)号：US06785447B2
公开(公告)日：2004-08-31
申请号：US09767582
申请日：2001-01-22
申请人： Tetsuzo Yoshimura , Yasuhito Takahashi , James Roman , Solomon I. Beilin , Wen-chou Vincent Wang , Masaaki Inao
发明人： Tetsuzo Yoshimura , Yasuhito Takahashi , James Roman , Solomon I. Beilin , Wen-chou Vincent Wang , Masaaki Inao
IPC分类号： G02B626
CPC分类号： G02B6/10 , G02B6/06 , G02B6/12002 , G02B6/124 , G02B6/13 , G02B6/132 , G02B6/136 , G02B6/26 , G02B6/42 , G02B6/4214 , G02B6/43 , G02B2006/12104 , G02B2006/12107 , G02B2006/12173 , H01L21/6835 , H01L23/48 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/167 , H01L2221/68345 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/24226 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01056 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/10336 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/18162 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3511 , H05K1/0274 , H05K1/14 , H01L2924/00 , H01L2224/05611 , H01L2924/00014 , H01L2224/05644 , H01L2224/05664
摘要： An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.
摘要翻译：一种用于反射遵循由光波导限定的路径的光信号的光反射结构，包括具有第一平面包层表面的第一包层; 布置在所述第一包层上的波导; 以及设置在波导上并具有第二平面包层表面的第二包覆层。第一包层，第二包层和波导终止于具有斜面平坦表面的大致鸽尾结构中。光反射器设置在倾斜平面上，用于通过波导的光信号的改变方向。公开了制造光反射结构的方法。

3. 发明授权

US6054761A Multi-layer circuit substrates and electrical assemblies having conductive composition connectors 有权
标题翻译：具有导电组合物连接器的多层电路基板和电气组件
公开(公告)号：US6054761A
公开(公告)日：2000-04-25
申请号：US203126
申请日：1998-12-01
申请人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
发明人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
IPC分类号： C08K3/00 , C08L63/00 , H01L23/498 , H05K3/40 , H05K3/46 , H01L23/04
CPC分类号： H05K3/363 , H01L23/49883 , H05K3/4069 , H05K3/4614 , H05K3/4617 , H05K3/462 , H01L2224/16503 , H05K2201/09536 , H05K2201/096 , H05K2201/09827 , H05K2201/10666 , H05K2203/0425 , H05K2203/0455 , H05K3/321 , H05K3/4623
摘要： Printed circuit substrates and electrical assemblies including a conductive composition are disclosed. The printed circuit substrate and the electrical assembly embodiments comprise a first conducting region and a second conducting region. A dielectric layer is disposed between the first and second conducting regions. An aperture is disposed in the dielectric layer and a via structure including the conductive composition is disposed in the aperture. The conductive composition is preferably in a cured state and electrically communicates with the first and second conducting regions. In preferred embodiments, the conductive composition comprises conductive particles in an amount of at least about 75 wt. % based on the weight of the composition. At least 50% by weight of the conductive particles have melting points of less than about 400.degree. C. The composition further includes a carrier including an epoxy-functional resin in an amount of at least about 50 wt. % based on the weight of the carrier, and a fluxing agent in an amount of at least about 0.1 wt % based on the weight of the carrier. The epoxy functional resin can have a viscosity of less than about 1000 centipoise at 25.degree. C.
摘要翻译：公开了印刷电路基板和包括导电组合物的电气组件。印刷电路基板和电组件实施例包括第一导电区域和第二导电区域。电介质层设置在第一和第二导电区域之间。在电介质层中设置孔，并且包括导电组合物的通孔结构设置在孔中。导电组合物优选处于固化状态并与第一和第二导电区域电连通。在优选的实施方案中，导电组合物包含至少约75wt。基于组合物的重量％。至少50重量％的导电颗粒具有小于约400℃的熔点。该组合物还包括载体，其包含至少约50重量％的量的环氧官能树脂。基于载体的重量，以及基于载体重量的至少约0.1重量％的助熔剂。环氧官能树脂在25℃下的粘度可以小于约1000厘泊

4. 发明授权

US06281040B1 Methods for making circuit substrates and electrical assemblies 有权
标题翻译：制造电路基板和电气组件的方法
公开(公告)号：US06281040B1
公开(公告)日：2001-08-28
申请号：US09397614
申请日：1999-09-16
申请人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
发明人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
IPC分类号： H01L2144
CPC分类号： H05K3/363 , H01L23/49883 , H01L2224/16503 , H05K3/321 , H05K3/4069 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2201/09827 , H05K2201/10666 , H05K2203/0425 , H05K2203/0455
摘要： Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.
摘要翻译：公开了制造电路基板和电气组件的方法。导电组合物设置在相对的导电区域之间，并且可以被固化以形成通孔结构。导电组合物包括导电颗粒和载体。载体可以包括助熔剂和在25℃下粘度小于约1000厘泊的环氧官能树脂。

5. 发明授权

US06579474B2 Conductive composition 失效
标题翻译：导电组成
公开(公告)号：US06579474B2
公开(公告)日：2003-06-17
申请号：US09782384
申请日：2001-02-12
申请人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
发明人： Mark Thomas McCormack , Hunt Hang Jiang , Solomon I. Beilin , Albert Wong Chan , Yasuhito Takahashi
IPC分类号： H01B104
CPC分类号： H05K3/363 , H01L23/49883 , H01L2224/16503 , H05K3/321 , H05K3/4069 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2201/09827 , H05K2201/10666 , H05K2203/0425 , H05K2203/0455
摘要： A conductive composition, and articles and methods using the conductive composition are disclosed.
摘要翻译：公开了导电组合物，以及使用导电组合物的制品和方法。

6. 发明授权

US06106923A Venting hole designs for multilayer conductor-dielectric structures 失效
标题翻译：多孔导体介质结构的通孔设计
公开(公告)号：US06106923A
公开(公告)日：2000-08-22
申请号：US859642
申请日：1997-05-20
申请人： Yasuhito Takahashi , Solomon I. Beilin , Michael G. Peters
发明人： Yasuhito Takahashi , Solomon I. Beilin , Michael G. Peters
IPC分类号： H05K3/46 , H01L23/12 , H01L23/538 , H05K1/02 , B32B3/10 , H01L23/48 , H05K1/00
CPC分类号： H01L23/5383 , H01L23/5386 , H05K1/0224 , H01L2924/0002 , H01L2924/3011 , H05K1/0253 , H05K2201/062 , H05K2201/09681 , H05K2203/1178 , H05K3/4644 , Y10T428/24273 , Y10T428/24298 , Y10T428/24314 , Y10T428/24322 , Y10T428/24331
摘要： Disclosed are venting hole structures suitable for AC grounding planes in multichip modules (MCMs) and the like. Such structures may be constructed from alternating layers of metal and dielectric materials, such as copper and polyimide, respectively. The venting structures according to the present invention are formed in the metal layers of grounding planes and enable gases trapped within the underlying dielectric layers to escape (so as to prevent delamination) without disturbing the function of the AC grounding plane to provide controlled impedance characteristics for signal lines disposed above and below the grounding plane.
摘要翻译：公开了适用于多芯片模块（MCM）等中的交流接地平面的排气孔结构。这种结构可以分别由金属和电介质材料的交替层构成，例如铜和聚酰亚胺。根据本发明的排气结构形成在接地平面的金属层中，并且使得被捕获在下面的介电层内的气体能够逸出（以防止分层），而不会干扰AC接地平面的功能，从而为设置在接地平面上方和下方的信号线。

7. 发明授权

US5872696A Sputtered and anodized capacitors capable of withstanding exposure to high temperatures 失效
标题翻译：溅射和阳极氧化电容器能承受高温暴露
公开(公告)号：US5872696A
公开(公告)日：1999-02-16
申请号：US826980
申请日：1997-04-09
申请人： Michael G. Peters , Michael G. Lee , Solomon I. Beilin , Yasuhito Takahashi
发明人： Michael G. Peters , Michael G. Lee , Solomon I. Beilin , Yasuhito Takahashi
IPC分类号： H01G4/08 , H01L21/02 , H01G4/008 , B05D5/12 , H01G4/06
CPC分类号： H01L28/60 , H01G4/085
摘要： Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride. The tantalum nitride layer was discovered by the inventors to act as a good high temperature diffusion barrier for the aluminum, preventing the aluminum from migrating into the anodized tantalum pentoxide layer under high temperature processing conditions, where it would chemically reduce the tantalum atoms in the tantalum pentoxide layer and introduce conductive paths of tantalum in the dielectric (tantalum pentoxide) layer. The aluminum layer provides good electrical conductivity for the bottom electrode, and is anodized to fill any pinhole defects in the layers formed above it, thereby increasing manufacturing yields.
摘要翻译：公开了一种电容器的新型结构，其能够耐热处理至少400℃，同时在其电极中提供低缺陷密度和低电串联电阻。在本发明的一个实施例中，电容器结构包括由铝的第一子层，氮化钽的第二子层和钽的第三子层形成的底部电容器电极。电容器结构还包括在底部电极的钽子层上的五氧化二钽的溅射介电层。所得到的结构被阳极氧化，使得下面的钽层被完全阳极氧化，并且优选地使得一部分氮化钽层转化为氮氧化钽。本发明人发现氮化钽层用作铝的良好的高温扩散阻挡层，防止铝在高温加工条件下迁移到阳极氧化的五氧化二钽层中，其中它将化学还原钽中的钽原子并在介电（五氧化二钽）层中引入钽的导电路径。铝层为底部电极提供良好的导电性，并被阳极氧化以填充其上形成的层中的任何针孔缺陷，从而提高制造产量。

8. 发明授权

US06226171B1 Power conducting substrates with high-yield integrated substrate capacitor 有权
标题翻译：具有高成本集成基板电容器的导电基板
公开(公告)号：US06226171B1
公开(公告)日：2001-05-01
申请号：US09227239
申请日：1999-01-08
申请人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
发明人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
IPC分类号： H01G4228
CPC分类号： H01L23/50 , H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/056 , H05K1/162 , H05K3/045 , H05K3/388 , H05K3/44 , H05K2201/0154 , H05K2201/0195 , H05K2201/09481 , H05K2201/09509 , H05K2201/09554 , H05K2203/0315 , H01L2924/00
摘要： Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.
摘要翻译：公开了用于增加基板电容器的产量的几个发明特征。本发明的特征涉及在电容器的主介电层的选定区域周围选择性地放置绝缘层和贴片。这些绝缘层和缺陷防止某些制造处理步骤在主介电层中产生针孔缺陷。本发明的特征适合于用于主介电层的任何类型的材料，并且特别适用于阳极化电介质层。

9. 发明授权

US06239485B1 Reduced cross-talk noise high density signal interposer with power and ground wrap 失效
标题翻译：减少串扰噪声高密度信号插入器与电源和地面包装
公开(公告)号：US06239485B1
公开(公告)日：2001-05-29
申请号：US09315785
申请日：1999-05-20
申请人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
发明人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
IPC分类号： H01L2312
CPC分类号： H05K1/0219 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L23/552 , H01L2224/16225 , H01L2224/16235 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/141 , H05K1/144 , H05K3/20 , H05K2201/049 , H05K2201/055 , H05K2201/10378 , H01L2924/00
摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
摘要翻译：一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。本发明的插入器包括信号芯和外部电源/接地连接外壳。这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。信号芯由位于两个电介质层之间的导电电源/接地平面形成。在每个电介质层上形成图案化的金属层。两个金属层通过通孔或后处理相互连接。导电功率/接地面用于减少形成在两个图案化金属层上的信号线之间的信号串扰。电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。电源/接地线圈的上下基板由两面具有图案化金属层的电介质膜形成，图案化层通过通孔或后工艺连接。两个电源/接地包覆基板可以分开地形成，或者可以从弯曲成所需形状（例如，“U”形状）的一个基板形成。两个电源/接地基板相对于信号芯线保持正确的对准，并通过也连接到信号芯的中间电源/接地平面的边缘连接器彼此保持。

10. 发明授权

US06428942B1 Multilayer circuit structure build up method 失效
标题翻译：多层电路结构建立方法
公开(公告)号：US06428942B1
公开(公告)日：2002-08-06
申请号：US09429854
申请日：1999-10-28
申请人： Hunt Hang Jiang , Yasuhito Takahashi , Michael Guang-Tzong Lee , Wen-chou Vincent Wang , Mark McCormack
发明人： Hunt Hang Jiang , Yasuhito Takahashi , Michael Guang-Tzong Lee , Wen-chou Vincent Wang , Mark McCormack
IPC分类号： G03F700
CPC分类号： H01L24/96 , H01L21/486 , H01L2221/68359 , H01L2224/16237 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/12042 , H01L2924/3011 , H05K3/0035 , H05K3/108 , H05K3/243 , H05K3/4602 , H05K3/4647 , H05K2203/066 , H05K2203/0733 , H05K2203/1383 , H01L2924/00
摘要： Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.
摘要翻译：公开了形成多层电路结构的方法。在一些实施例中，可以在电路化芯结构的两侧上形成导电层，电介质层和导电柱。导电柱设置在电介质层中并且可以被堆叠以形成通常至少部分穿过多层电路结构的大致垂直的传导路径。形成的多层电路结构可以占据比具有堆叠通孔结构的相应多层电路结构更小的空间。

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