会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明授权
    • Semiconductor device including multi-layer conductive thin film of
polycrystalline material
    • 半导体器件包括多层导电薄膜的多晶材料
    • US5444302A
    • 1995-08-22
    • US168506
    • 1993-12-22
    • Takashi NakajimaHideo MiuraHiroyuki OhtaNoriaki Okamoto
    • Takashi NakajimaHideo MiuraHiroyuki OhtaNoriaki Okamoto
    • H01L21/02H01L23/532H01L29/49H01L23/48H01L29/46
    • H01L21/28097H01L21/28035H01L21/28518H01L21/28525H01L21/32053H01L21/76838H01L21/76877H01L21/823437H01L23/485H01L23/53257H01L23/53271H01L28/40H01L29/4925H01L29/4975H01L2924/0002Y10T117/10Y10T117/1004
    • In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
    • 例如,通过氧化硅膜5在半导体衬底4上的硅6氧化膜5上形成电极2时,栅电极2被构成为多个多晶硅层6的层叠结构。 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶(再结晶)的方法形成栅电极2。 在这种情况下,非晶层的沉积被分开多次进行,使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后,非晶材料结晶,重复沉积非晶层的过程和结晶非晶材料的过程,由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构,可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生,层中的裂纹等,并且可以获得 通过多晶材料的层叠,具有所需膜厚度的小晶粒尺寸的多晶层。
    • 8. 发明申请
    • Method of manufacturing semiconductor device having conductive thin films
    • 制造具有导电薄膜的半导体器件的方法
    • US20060252186A1
    • 2006-11-09
    • US11480912
    • 2006-07-06
    • Takashi NakajimaHideo MiuraHiroyuki OhtaNoriaki Okamoto
    • Takashi NakajimaHideo MiuraHiroyuki OhtaNoriaki Okamoto
    • H01L21/84
    • H01L21/28097H01L21/28035H01L21/28518H01L21/28525H01L21/32053H01L21/76838H01L21/76877H01L21/823437H01L23/485H01L23/53257H01L23/53271H01L28/40H01L29/4925H01L29/4975H01L2924/0002Y10T117/10Y10T117/1004H01L2924/00
    • In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
    • 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时,例如,栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶(再结晶)的方法形成。 在这种情况下,非晶层的沉积被分开多次进行,使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后,非晶材料结晶,重复沉积非晶层的过程和结晶非晶材料的过程,由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构,可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生,层中的裂纹等,并且可以获得 通过多晶材料的层叠,具有所需膜厚度的小晶粒尺寸的多晶层。
    • 9. 发明授权
    • Low stress semiconductor devices with thermal oxide isolation
    • 具有热氧化隔离的低应力半导体器件
    • US06310384B1
    • 2001-10-30
    • US08838259
    • 1997-04-17
    • Hideo MiuraMakoto OgasawaraHiroo MasudaJun MurataNoriaki Okamoto
    • Hideo MiuraMakoto OgasawaraHiroo MasudaJun MurataNoriaki Okamoto
    • H01L2900
    • H01L21/76205H01L21/76202H01L27/0802
    • A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.
    • 确定电路器件隔离区域的宽度和形成在半导体衬底上的器件区域的宽度,以满足防止由于形成隔离区域的热氧化引起的位错发生的条件。 根据制造方案,制造的半导体器件包括半导体衬底,形成在半导体衬底中的器件形成区域上并具有0.1至125μm的宽度的多个电路区域和形成在半导体衬底上的器件隔离区域 以便将多个电路区彼此隔离并且具有0.01至2.5μm的宽度。 在这种设计的器件中,器件区域的宽度与器件隔离区域的宽度的比率为2至50.每个器件隔离区域是通过在衬底氧化物中蚀刻一部分而形成在半导体衬底中的沟槽 形成在半导体衬底的表面上的膜和形成在衬垫氧化膜上的氮化物膜,存在于器件隔离区上,并且当从半导体上的衬垫氧化物膜的位置测量时具有0至10nm的深度 基质。