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1. 发明公开

US20230353157A1 PEROVSKITE-BASED MAGNETOELECTRIC SPIN-ORBIT LOGIC DEVICES 审中-公开
公开(公告)号：US20230353157A1
公开(公告)日：2023-11-02
申请号：US17733166
申请日：2022-04-29
申请人： Tanay A. Gosavi , Chia-Ching Lin , Sasikanth Manipatruni , Dmitri Evgenievich Nikonov , Ian Alexander Young , Ramamoorthy Ramesh , Darrell G. Schlom , Megan E. Holtz , Rachel A. Steinhardt
发明人： Tanay A. Gosavi , Chia-Ching Lin , Sasikanth Manipatruni , Dmitri Evgenievich Nikonov , Ian Alexander Young , Ramamoorthy Ramesh , Darrell G. Schlom , Megan E. Holtz , Rachel A. Steinhardt
IPC分类号： H03K19/18 , H01L43/10 , H01L43/02 , H01L27/22
CPC分类号： H03K19/18 , H01L43/10 , H01L43/02 , H01L27/22
摘要： Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

2. 发明申请

US20160377669A1 ON-CHIP TEST CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) 审中-公开
标题翻译：用于磁性随机存取存储器的片上测试电路（MRAM）
公开(公告)号：US20160377669A1
公开(公告)日：2016-12-29
申请号：US14749324
申请日：2015-06-24
申请人： Sasikanth Manipatruni , Chia-Ching Lin , Yih Wang , Ian A. Young
发明人： Sasikanth Manipatruni , Chia-Ching Lin , Yih Wang , Ian A. Young
IPC分类号： G01R31/12 , G11C29/00 , G01R29/26 , G11C11/16
CPC分类号： G01R29/26 , G01R31/129 , G01R31/2879 , G11C11/1697 , G11C29/50 , G11C2029/5002
摘要： Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.
摘要翻译：实施例包括用于测试磁随机存取存储器（MRAM）的一个或多个磁隧道结（MTJ）的测试电路。测试电路可以测量时域中的MTJ的1 / f噪声，并确定1 / f噪声的功率谱密度（PSD）。测试电路可以基于PSD估计MTJ和/或MRAM的一个或多个参数。例如，测试电路可以基于PSD来确定诸如Hooge alpha参数的噪声参数，并且可以基于1 / f参数估计MTJ和/或MRAM的一个或多个参数。可以描述和要求保护其他实施例。

3. 发明授权

US10825509B2 Full-rail digital read compute-in-memory circuit 有权
公开(公告)号：US10825509B2
公开(公告)日：2020-11-03
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
发明人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
IPC分类号： G11C11/00 , G11C11/419 , G11C27/02 , G11C7/10 , G11C7/12 , G11C11/412 , G11C11/418
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

4. 发明申请

US20200091414A1 MAGNETOELECTRIC SPIN ORBIT LOGIC BASED FULL ADDER 审中-公开
公开(公告)号：US20200091414A1
公开(公告)日：2020-03-19
申请号：US16130912
申请日：2018-09-13
申请人： Huichu Liu , Sasikanth Manipatruni , Daniel Morris , Kaushik Vaidyanathan , Tanay Karnik , Ian Young
发明人： Huichu Liu , Sasikanth Manipatruni , Daniel Morris , Kaushik Vaidyanathan , Tanay Karnik , Ian Young
IPC分类号： H01L43/04 , H01L43/06 , H01L43/10 , G11C11/16 , G11C11/18
摘要： An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

5. 发明申请

US20190057050A1 PIPELINE CIRCUIT ARCHITECTURE TO PROVIDE IN-MEMORY COMPUTATION FUNCTIONALITY 审中-公开
公开(公告)号：US20190057050A1
公开(公告)日：2019-02-21
申请号：US16160952
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor W. Lee , Abhishek Sharma , Huseyin E. Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , Ian Young
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor W. Lee , Abhishek Sharma , Huseyin E. Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , Ian Young
IPC分类号： G06F13/16 , G06F13/28
摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

6. 发明授权

US09711284B2 Structure to make supercapacitor 有权
公开(公告)号：US09711284B2
公开(公告)日：2017-07-18
申请号：US13711531
申请日：2012-12-11
申请人： Brian S. Doyle , Sasikanth Manipatruni , Shawna M. Liff , Vivek K. Singh
发明人： Brian S. Doyle , Sasikanth Manipatruni , Shawna M. Liff , Vivek K. Singh
IPC分类号： H01G4/16 , H01G4/30 , H01G4/28 , H01L29/06 , H01G4/008 , B82Y10/00 , H01L49/02 , D03D1/00 , H01L29/775
CPC分类号： H01G4/008 , B82Y10/00 , D03D1/0088 , D10B2401/18 , H01G4/28 , H01L28/60 , H01L29/0673 , H01L29/068 , H01L29/775 , Y02E60/13
摘要： A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.

7. 发明授权

US08988109B2 High speed precessionally switched magnetic logic 有权
标题翻译：高速切换磁逻辑
公开(公告)号：US08988109B2
公开(公告)日：2015-03-24
申请号：US13678877
申请日：2012-11-16
申请人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： H03K17/16 , H03K19/16
CPC分类号： H03K19/16 , G11C11/16 , G11C11/161 , H01F10/3268 , H03K17/80
摘要： High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.
摘要翻译：描述了高速开关磁逻辑器件和架构。在第一示例中，磁逻辑器件包括具有第一纳米磁体的输入电极和具有第二纳米磁体的输出电极。第二纳米磁体的自旋与第一纳米磁体的自旋不共线。沟道区域和对应的接地电极设置在输入和输出电极之间。在第二示例中，磁逻辑器件包括具有面内纳米磁体的输入电极和具有垂直磁各向异性（PMA）磁体的输出电极。沟道区域和对应的接地电极设置在输入和输出电极之间。

8. 发明申请

US20140292429A1 MULTIGATE RESONANT CHANNEL TRANSISTOR 有权
标题翻译：多通道谐振通道晶体管
公开(公告)号：US20140292429A1
公开(公告)日：2014-10-02
申请号：US13994714
申请日：2013-03-28
申请人： Sasikanth Manipatruni , Raseong Kim , Rajashree Baskaran , Rajeev K. Dokania , Ian A. Young
发明人： Sasikanth Manipatruni , Raseong Kim , Rajashree Baskaran , Rajeev K. Dokania , Ian A. Young
IPC分类号： B81B3/00 , H03B5/30 , B81C1/00
CPC分类号： H03B5/30 , H01L29/66795 , H01L29/7831 , H01L2924/13067 , H01L2924/13084
摘要： An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.
摘要翻译：实施例包括：振荡器，包括形成在基板上的放大器; 形成在所述衬底上的多栅极共振沟道阵列包括：（a）包括鳍片的晶体管，每个鳍片在源极和漏极节点之间具有耦合到共源极和漏极触点的沟道; 和（b）共同的第一和第二三栅极，其耦合到每个散热片并且位于源极和漏极接触之间; 其中当第一和第二三门中的一个被周期性地激活以在翅片上产生周期性向下的力时，翅片以第一频率机械共振。其他实施例包括在源极和漏极节点之间具有沟道的非平面晶体管和鳍上的三栅极; 其中当所述第一三栅极被周期性地激活以在所述散热片上产生周期性向下的力时，所述翅片机械谐振。本文描述了其它实施例。

9. 发明申请

US20140173716A1 METHOD AND APPARATUS FOR MANAGING AND ACCESSING PERSONAL DATA 有权
标题翻译：用于管理和访问个人数据的方法和装置
公开(公告)号：US20140173716A1
公开(公告)日：2014-06-19
申请号：US13717433
申请日：2012-12-17
申请人： Sasikanth Manipatruni , Kelin J. Kuhn , Debendra Mallik , John C. Johnson
发明人： Sasikanth Manipatruni , Kelin J. Kuhn , Debendra Mallik , John C. Johnson
IPC分类号： G06F21/44
CPC分类号： G06F21/44 , G06F21/10 , G06F21/35
摘要： Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.
摘要翻译：描述管理和访问个人数据。在一个示例中，设备具有应用处理器，用于存储数据的存储器，耦合到应用处理器的接收和发送阵列，以接收存储在存储器中的数据并通过无线接口传输存储在存储器中的数据，以及惯性传感器，用于接收用户命令，以授权处理器通过接收和发送阵列接收和发送数据。

10. 发明申请

US20140170919A1 FLEXIBLE EMBEDDED INTERCONNECTS 有权
标题翻译：灵活嵌入式互联
公开(公告)号：US20140170919A1
公开(公告)日：2014-06-19
申请号：US13714990
申请日：2012-12-14
申请人： Sasikanth Manipatruni , Brian S. Doyle , Shawna M. Liff , Vivek K. Singh
发明人： Sasikanth Manipatruni , Brian S. Doyle , Shawna M. Liff , Vivek K. Singh
IPC分类号： D03D1/00 , H01B7/04 , D01D5/04 , B21C3/00 , D04H3/00 , D02G3/44
CPC分类号： D03D1/0088 , B21C23/08 , B21C37/042 , B21C37/047 , D01D5/00 , D01D5/34 , D02G3/441 , D04H1/4266 , D04H1/4382 , D04H3/00 , D10B2401/16 , D10B2401/18 , Y10T442/3057 , Y10T442/603
摘要： Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.
摘要翻译：描述了允许在传统织物中放置电子功能的柔性电子功能纤维。纤维可与天然纤维交织以产生可保持其原始外观的电功能织物和装置。

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