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1. 发明授权

US10360496B2 Apparatus and method for a digital neuromorphic processor 有权
公开(公告)号：US10360496B2
公开(公告)日：2019-07-23
申请号：US15088543
申请日：2016-04-01
申请人： Gregory K. Chen , Jae-Sun Seo , Thomas C Chen , Raghavan Kumar
发明人： Gregory K. Chen , Jae-Sun Seo , Thomas C Chen , Raghavan Kumar
IPC分类号： G06N3/063 , G06N3/04
摘要： An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.

2. 发明申请

US20170286827A1 APPARATUS AND METHOD FOR A DIGITAL NEUROMORPHIC PROCESSOR 审中-公开
公开(公告)号：US20170286827A1
公开(公告)日：2017-10-05
申请号：US15088543
申请日：2016-04-01
申请人： GREGORY K. CHEN , JAE-SUN SEO , THOMAS C CHEN , RAGHAVAN KUMAR
发明人： GREGORY K. CHEN , JAE-SUN SEO , THOMAS C CHEN , RAGHAVAN KUMAR
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/049
摘要： An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.

3. 发明申请

US20170185888A1 Interconnection Scheme for Reconfigurable Neuromorphic Hardware 审中-公开
公开(公告)号：US20170185888A1
公开(公告)日：2017-06-29
申请号：US14757397
申请日：2015-12-23
申请人： Gregory K. Chen , Jae-Sun Seo
发明人： Gregory K. Chen , Jae-Sun Seo
IPC分类号： G06N3/063 , G06F9/445 , G06F13/42 , G06N3/04
CPC分类号： G06N3/04 , G06F13/4282 , G06N3/02 , G06N3/063
摘要： Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

4. 发明申请

US20150220470A1 METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 有权
标题翻译：用于芯片上同步电路切换网络的方法，装置和系统（NOC）
公开(公告)号：US20150220470A1
公开(公告)日：2015-08-06
申请号：US14126910
申请日：2013-06-28
申请人： Gregory K. Chen , Mark A. Anders , Himanshu Kaul , Sudhir K. Satpathy , Ram K. Krishnamurthy
发明人： Gregory K. Chen , Mark A. Anders , Himanshu Kaul , Sudhir K. Satpathy , Ram K. Krishnamurthy
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。描述和要求保护其他实施例。

5. 发明授权

US08593171B2 Power supply monitor 有权
标题翻译：电源监视器
公开(公告)号：US08593171B2
公开(公告)日：2013-11-26
申请号：US12950584
申请日：2010-11-19
申请人： Stephen V. Kosonocky , Gregory K. Chen
发明人： Stephen V. Kosonocky , Gregory K. Chen
IPC分类号： G01R31/40
CPC分类号： G01R31/40
摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.
摘要翻译：通过逐周期监测环形振荡器的性能来测量电源变化和抖动。通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。

6. 发明授权

US10825509B2 Full-rail digital read compute-in-memory circuit 有权
公开(公告)号：US10825509B2
公开(公告)日：2020-11-03
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
发明人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
IPC分类号： G11C11/00 , G11C11/419 , G11C27/02 , G11C7/10 , G11C7/12 , G11C11/412 , G11C11/418
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

7. 发明申请

US20150071282A1 ARCHITECTURE AND METHOD FOR HYBRID CIRCUIT-SWITCHED AND PACKET-SWITCHED ROUTER 有权
标题翻译：用于混合电路切换和分组交换路由器的架构和方法
公开(公告)号：US20150071282A1
公开(公告)日：2015-03-12
申请号：US14129544
申请日：2013-09-06
申请人： Mark A. Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
发明人： Mark A. Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
IPC分类号： H04L12/64
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.
摘要翻译：用于执行电路交换路由和分组交换路由以用于网络通信的技术和机制。在一个实施例中，路由器评估由路由器接收的分组的控制信息，评估以检测分组是否包括用于边带通信的数据。基于该评估，路由器从路由器的多个模式中进行选择，该多个模式包括在网络中路由用于边带数据的分组交换通信的分组的第一模式。多个模式还包括根据分组配置电路交换信道的第二模式。在另一个实施例中，路由器确定用于在分层网络中路由分组的方向，其中所述方向的确定基于所述分级网络的层级中的路由器的级别。

8. 发明申请

US20200098824A1 DIODE BASED RESISTIVE RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：US20200098824A1
公开(公告)日：2020-03-26
申请号：US16142040
申请日：2018-09-26
申请人： Abhishek SHARMA , Gregory K. CHEN , Ram KRISHNAMURTHY , Ravi PILLARISETTY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Urusa ALAAN , Noriyuki SATO
发明人： Abhishek SHARMA , Gregory K. CHEN , Ram KRISHNAMURTHY , Ravi PILLARISETTY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Urusa ALAAN , Noriyuki SATO
IPC分类号： H01L27/24 , H01L45/00
摘要： Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.

9. 发明授权

US09634866B2 Architecture and method for hybrid circuit-switched and packet-switched router 有权
公开(公告)号：US09634866B2
公开(公告)日：2017-04-25
申请号：US14129544
申请日：2013-09-06
申请人： Mark A Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
发明人： Mark A Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
IPC分类号： H04L12/64 , H04L12/933
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.

10. 发明申请

US20190103156A1 FULL-RAIL DIGITAL READ COMPUTE-IN-MEMORY CIRCUIT 审中-公开
公开(公告)号：US20190103156A1
公开(公告)日：2019-04-04
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
发明人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/12 , G11C11/412 , G11C11/418 , G11C27/024
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

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