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1. 发明授权

US5295653A Vibration insulator having bracket 失效
标题翻译：振动绝缘子带支架
公开(公告)号：US5295653A
公开(公告)日：1994-03-22
申请号：US955440
申请日：1992-10-02
申请人： Takeshi Miyazaki , Tetsuya Takamori , Yutaka Ogasawara , Minoru Yamashita , Takaharu Shibuya
发明人： Takeshi Miyazaki , Tetsuya Takamori , Yutaka Ogasawara , Minoru Yamashita , Takaharu Shibuya
IPC分类号： B21D53/00 , B60G7/00 , F16F1/38 , F16F1/387 , F16M3/00
CPC分类号： F16F1/3849 , B21D53/00 , B60G7/00 , F16F1/387
摘要： vibration insulator is provided which includes a vibration insulator section having an outer cylinder, a rubber member which is vulcanization-bonded to the inner peripheral surface of the outer cylinder and an inner cylinder supported by the rubber member, and a bracket for supporting the vibration insulator section, with the thickness of the bracket material being made as small as possible. The bracket is composed of a pair of sheet-metal bracket members holding the axial ends of the vibration insulator. The bracket members include plate-like base sections axially opposed to each other, cylindrical sections which extend axially outward from the base sections and into which the end portions of the outer cylinder are forced, abutting sections extending radially inward from the end edges of the cylindrical sections and abutting the end surfaces of the outer cylinder and joint sections joining the bracket members to each other. A method of manufacturing the vibration insulator bracket is also provided.
摘要翻译：提供了一种振动绝缘体，其包括具有外筒的橡胶构件，和外筒的内周面硫化的橡胶构件和由橡胶构件支承的内筒的振动绝缘体，以及用于将振动绝缘体支架材料的厚度尽可能小。支架由保持振动绝缘体的轴向端的一对金属板支架构件组成。托架构件包括彼此轴向相对的板状基部，从基部轴向向外延伸并且外筒的端部被迫动的圆柱形部分，邻接部分从圆柱形的端部边缘径向向内延伸并且将外筒的端面和将托架构件彼此接合的接合部邻接。还提供了一种制造振动绝缘支架的方法。

2. 发明授权

US07307894B2 Semiconductor device and control method of the same 有权
标题翻译：半导体器件及其控制方法相同
公开(公告)号：US07307894B2
公开(公告)日：2007-12-11
申请号：US11127712
申请日：2005-05-12
申请人： Kazunari Kido , Kazuhiro Kurihara , Minoru Yamashita
发明人： Kazunari Kido , Kazuhiro Kurihara , Minoru Yamashita
IPC分类号： G11C7/10
CPC分类号： G11C16/22 , G11C15/00 , G11C15/04
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译：半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。

3. 发明申请

US20050254316A1 Semiconductor device and control method of the same 有权
标题翻译：半导体器件及其控制方法相同
公开(公告)号：US20050254316A1
公开(公告)日：2005-11-17
申请号：US11127712
申请日：2005-05-12
申请人： Kazunari Kido , Kazuhiro Kurihara , Minoru Yamashita
发明人： Kazunari Kido , Kazuhiro Kurihara , Minoru Yamashita
IPC分类号： G11C5/00 , G11C15/00 , G11C15/04 , G11C16/22
CPC分类号： G11C16/22 , G11C15/00 , G11C15/04
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译：半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。

4. 发明申请

US20050000604A1 Aluminum alloy, cast article of aluminum alloy, and method for producing cast article of aluminum alloy 审中-公开
标题翻译：铝合金，铝合金铸件和铝合金铸造件的制造方法
公开(公告)号：US20050000604A1
公开(公告)日：2005-01-06
申请号：US10487940
申请日：2002-08-30
申请人： Hiroshi Kawahara , Yoshihiro Shimizu , Yoshio Sugiyama , Toshio Horie , Hiroaki Iwahori , Yoshihiko Sugimoto , Minoru Yamashita
发明人： Hiroshi Kawahara , Yoshihiro Shimizu , Yoshio Sugiyama , Toshio Horie , Hiroaki Iwahori , Yoshihiko Sugimoto , Minoru Yamashita
IPC分类号： B22D21/00 , C22C21/06
CPC分类号： C22C21/06 , B22D21/007
摘要： An aluminum alloy according to the present invention includes from 4.0 to 6.0% Mg, from 0.3 to 0.6% Mn, from 0.5 to 0.9% Fe, and the balance of Al and inevitable impurities when the entirety is taken as 100% by mass. By appropriately selecting the composition range of Mg, Mn and Fe, it has been possible to micro-finely crystallize Al (Mn, Fe) compounds while inhibiting the growth of primary-crystal Al. As a result, the resulting aluminum alloy is good in terms of the castability, and shows high strength as well as high ductility.
摘要翻译：本发明的铝合金包含4.0〜6.0％的Mg，0.3〜0.6％的Mn，0.5〜0.9％的Fe，当全部为100质量％时，其余为Al和不可避免的杂质。通过适当选择Mg，Mn和Fe的组成范围，可以在抑制一次晶体Al的生长的同时微细微细化Al（Mn，Fe）化合物。结果，所得铝合金在铸造性方面是良好的，并且显示出高强度以及高延展性。

5. 发明授权

US6014329A Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US6014329A
公开(公告)日：2000-01-11
申请号：US986337
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

6. 发明授权

US5452251A Semiconductor memory device for selecting and deselecting blocks of word lines 失效
标题翻译：用于选择和取消选择字线块的半导体存储器件
公开(公告)号：US5452251A
公开(公告)日：1995-09-19
申请号：US79738
申请日：1993-06-22
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C5/14 , G11C7/06 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/40
CPC分类号： G11C29/80 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C2029/5004 , G11C29/88
摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
摘要翻译：半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

7. 发明申请

US20070298784A1 Information processing device 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20070298784A1
公开(公告)日：2007-12-27
申请号：US11589506
申请日：2006-10-30
申请人： Minoru Yamashita , Takato Yokouchi , Tadatsugu Kotani , Kazuo Maehara , Yuji Fujimoto
发明人： Minoru Yamashita , Takato Yokouchi , Tadatsugu Kotani , Kazuo Maehara , Yuji Fujimoto
IPC分类号： H04Q7/20
CPC分类号： H04M1/236 , H04M1/0214 , H04M1/72522 , H04M1/72558 , H04M1/72583 , H04M2250/16 , H04M2250/52
摘要： According to an aspect of the invention, there is provided an information processing device including: a display unit configured to display a plurality of setting informations of a setting of function indicated by indication information displayed on a standby screen; a key unit configured to accept a selection of one piece of setting information among the plurality of setting informations; a control unit configured to cancel or change function setting, based on the setting information of which the selection is accepted by the key unit; and a display control unit configured to control a display of the indication information, which is performed by the display unit, in accordance with the cancel or the change of function setting performed by the control unit.
摘要翻译：根据本发明的一个方面，提供了一种信息处理设备，包括：显示单元，被配置为显示由待机屏幕上显示的指示信息所指示的功能设置的多个设置信息; 键单元，被配置为接受所述多个设置信息中的一条设置信息的选择; 控制单元，被配置为基于所述选择被所述键单元接受的设置信息来取消或改变功能设置; 以及显示控制单元，被配置为根据由控制单元执行的功能设置的取消或改变来控制由显示单元执行的指示信息的显示。

8. 发明授权

US06934194B2 Nonvolatile memory having a trap layer 有权
标题翻译：具有陷阱层的非易失性存储器
公开(公告)号：US06934194B2
公开(公告)日：2005-08-23
申请号：US10631812
申请日：2003-08-01
申请人： Satoshi Takahashi , Minoru Yamashita
发明人： Satoshi Takahashi , Minoru Yamashita
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475
摘要： A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.
摘要翻译：非易失性存储器具有多个存储单元，每个存储单元具有第一和第二源极/漏极区域，控制栅极和绝缘陷阱层，其设置在控制栅极和位于第一和/ 第二源/漏区。捕获层包括靠近第一源极/漏极区域的使用位区域，用于根据要被捕获的电荷的存在或不存在来存储数据，以及靠近第二源极/漏极区域的不使用位区域，其中在使用位区域中保持数据时电荷被捕获。优选地，在擦除操作完成的状态下，不使用位区域进入电荷被捕获的状态。

9. 发明授权

US06914824B2 Non-volatile semiconductor memory that is based on a virtual ground method 有权
标题翻译：基于虚拟地面方法的非易失性半导体存储器
公开(公告)号：US06914824B2
公开(公告)日：2005-07-05
申请号：US10392912
申请日：2003-03-21
申请人： Minoru Yamashita , Yuichi Einaga , Kazunari Kido
发明人： Minoru Yamashita , Yuichi Einaga , Kazunari Kido
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0491 , G11C16/26
摘要： A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.
摘要翻译：一种半导体存储器，可以防止在读取时间减少余量。要读取的存储单元中的漏极与充电位线之间的浮置状态的位线在一定时间段内被充电。

10. 发明授权

US06807433B2 Mobile communication terminal with unanswered incoming-call notifying function 有权
标题翻译：移动通信终端具有未应答的来电通知功能
公开(公告)号：US06807433B2
公开(公告)日：2004-10-19
申请号：US10098318
申请日：2002-03-18
申请人： Hisashi Oota , Kiyoshi Wagai , Minoru Yamashita
发明人： Hisashi Oota , Kiyoshi Wagai , Minoru Yamashita
IPC分类号： H04B138
CPC分类号： H04M1/0245 , H04M1/0214 , H04M1/22 , H04M1/575 , H04M1/72519 , H04M19/048
摘要： A mobile communication terminal is provided with a light-emitting element for notifying an unanswered incoming call. When the cancellation of an incoming call is canceled in a state where an incoming call response operation has not been carried out, the mobile communication terminal is brought into the standby state and then the light-emitting element is caused to emit light.
摘要翻译：移动通信终端设置有用于通知未应答来电的发光元件。当在没有进行来电响应操作的状态下取消来电时，移动通信终端进入待机状态，然后使发光元件发光。

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